74 lines
1.5 KiB
Makefile
74 lines
1.5 KiB
Makefile
COMMENT = framework for Verilog RTL synthesis
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DISTNAME = yosys-0.9pl4081
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REVISION = 0
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GH_ACCOUNT = YosysHQ
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GH_PROJECT = yosys
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GH_COMMIT = 25de8faf10157ab0cb40f77c7cbf3143527c598e
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CATEGORIES = cad
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HOMEPAGE = http://www.clifford.at/yosys/
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MAINTAINER = Alessandro De Laurenzis <just22@atlantide.mooo.com>
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# ISC (yosys), MIT (MiniSat)
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PERMIT_PACKAGE = Yes
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WANTLIB += ${COMPILER_LIBCXX} ${MODTCL_WANTLIB} c m readline ffi z
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# C++11
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COMPILER = base-clang ports-gcc
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MODULES = lang/python \
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lang/tcl
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CONFIGURE_STYLE = none
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BUILD_DEPENDS = devel/bison \
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shells/bash
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RUN_DEPENDS = cad/abc \
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math/graphviz \
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graphics/xdot \
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shells/bash
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LIB_DEPENDS = ${MODTCL_LIB_DEPENDS} \
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devel/libffi
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TEST_DEPENDS = ${BUILD_PKGPATH} \
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cad/abc \
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lang/gawk \
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lang/iverilog \
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shells/bash
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USE_GMAKE = Yes
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MAKE_FLAGS = CXX="${CXX}" \
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LD="${CXX} -L${LOCALBASE}/lib" \
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PRETTY=0
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MAKE_ENV = ABCEXTERNAL=${LOCALBASE}/bin/abc \
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CXXFLAGS="${CXXFLAGS}" \
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TCL_VERSION="${MODTCL_LIB}" \
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TCL_INCLUDE="${MODTCL_INCDIR}"
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TEST_ENV = MAKE="${MAKE_PROGRAM}"
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FAKE_FLAGS = PREFIX="${TRUEPREFIX}"
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# the only gcc-specific things from "config-gcc" are setting CXX/LD, which
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# we override above
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do-configure:
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@${SUBST_CMD} ${WRKSRC}/kernel/yosys.cc
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@cd ${WRKBUILD} && exec env -i ${MAKE_ENV} ${MAKE_PROGRAM} config-gcc
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post-build:
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grep -rl "#!/bin/bash" ${WRKSRC} | \
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xargs sed -i 's,#!/bin/bash,#!${LOCALBASE}/bin/bash,'
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post-install:
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${MODPY_BIN} ${MODPY_LIBDIR}/compileall.py \
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${PREFIX}/share/yosys/python3
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.include <bsd.port.mk>
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