96c8a0f23f
OpenSTA is a gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats: - Verilog netlist - Liberty library - SDC timing constraints - SDF delay annotation - SPEF parasitics From Alessandro De Laurenzis; thanks! ok sthen@
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368 B
Plaintext
12 lines
368 B
Plaintext
OpenSTA is a gate level static timing verifier. As a stand-alone
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executable it can be used to verify the timing of a design using
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standard file formats:
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- Verilog netlist
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- Liberty library
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- SDC timing constraints
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- SDF delay annotation
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- SPEF parasitics
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OpenSTA uses a TCL command interpreter to read the design, specify
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timing constraints and print timing reports.
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