169 lines
7.0 KiB
Plaintext
169 lines
7.0 KiB
Plaintext
$OpenBSD: patch-lib_Target_Sparc_SparcInstr64Bit_td,v 1.1 2014/07/11 01:05:24 brad Exp $
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Sync up the SPARC backend up to commit r203424.
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--- lib/Target/Sparc/SparcInstr64Bit.td.orig Sun Jun 15 02:45:38 2014
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+++ lib/Target/Sparc/SparcInstr64Bit.td Sun Jun 15 02:57:59 2014
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@@ -235,7 +235,8 @@ def UDIVXri : F3_2<2, 0b001101,
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let Predicates = [Is64Bit] in {
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// 64-bit loads.
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-defm LDX : Load<"ldx", 0b001011, load, I64Regs, i64>;
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+let DecoderMethod = "DecodeLoadInt" in
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+ defm LDX : Load<"ldx", 0b001011, load, I64Regs, i64>;
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let mayLoad = 1, isCodeGenOnly = 1, isAsmParserOnly = 1 in
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def TLS_LDXrr : F3_1<3, 0b001011,
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@@ -270,10 +271,12 @@ def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDR
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def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
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// Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
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-defm LDSW : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>;
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+let DecoderMethod = "DecodeLoadInt" in
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+ defm LDSW : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>;
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// 64-bit stores.
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-defm STX : Store<"stx", 0b001110, store, I64Regs, i64>;
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+let DecoderMethod = "DecodeStoreInt" in
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+ defm STX : Store<"stx", 0b001110, store, I64Regs, i64>;
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// Truncating stores from i64 are identical to the i32 stores.
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def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
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@@ -294,14 +297,6 @@ def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:
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// 64-bit Conditionals.
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//===----------------------------------------------------------------------===//
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-// Conditional branch class on %xcc:
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-class XBranchSP<dag ins, string asmstr, list<dag> pattern>
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- : F2_3<0b001, 0b10, (outs), ins, asmstr, pattern> {
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- let isBranch = 1;
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- let isTerminator = 1;
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- let hasDelaySlot = 1;
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-}
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-
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//
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// Flag-setting instructions like subcc and addcc set both icc and xcc flags.
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// The icc flags correspond to the 32-bit result, and the xcc are for the
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@@ -312,14 +307,12 @@ class XBranchSP<dag ins, string asmstr, list<dag> patt
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let Predicates = [Is64Bit] in {
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-let Uses = [ICC] in
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-def BPXCC : XBranchSP<(ins brtarget:$imm19, CCOp:$cond),
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- "b$cond %xcc, $imm19",
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- [(SPbrxcc bb:$imm19, imm:$cond)]>;
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+let Uses = [ICC], cc = 0b10 in
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+ defm BPX : IPredBranch<"%xcc", [(SPbrxcc bb:$imm19, imm:$cond)]>;
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// Conditional moves on %xcc.
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let Uses = [ICC], Constraints = "$f = $rd" in {
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-let cc = 0b110 in {
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+let intcc = 1, cc = 0b10 in {
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def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),
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(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
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"mov$cond %xcc, $rs2, $rd",
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@@ -332,7 +325,7 @@ def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd),
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(SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>;
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} // cc
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-let opf_cc = 0b110 in {
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+let intcc = 1, opf_cc = 0b10 in {
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def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
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(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
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"fmovs$cond %xcc, $rs2, $rd",
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@@ -351,6 +344,84 @@ def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs
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} // opf_cc
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} // Uses, Constraints
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+// Branch On integer register with Prediction (BPr).
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+let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in
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+multiclass BranchOnReg<bits<3> cond, string OpcStr> {
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+ def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
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+ !strconcat(OpcStr, " $rs1, $imm16"), []>;
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+ def apt : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
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+ !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
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+ def napn : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
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+ !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
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+ def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
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+ !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
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+}
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+
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+multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> {
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+ def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
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+ (NAPT I64Regs:$rs1, bprtarget16:$imm16)>;
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+ def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"),
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+ (APT I64Regs:$rs1, bprtarget16:$imm16)>;
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+}
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+
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+defm BPZ : BranchOnReg<0b001, "brz">;
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+defm BPLEZ : BranchOnReg<0b010, "brlez">;
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+defm BPLZ : BranchOnReg<0b011, "brlz">;
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+defm BPNZ : BranchOnReg<0b101, "brnz">;
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+defm BPGZ : BranchOnReg<0b110, "brgz">;
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+defm BPGEZ : BranchOnReg<0b111, "brgez">;
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+
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+defm : bpr_alias<"brz", BPZnapt, BPZapt >;
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+defm : bpr_alias<"brlez", BPLEZnapt, BPLEZapt>;
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+defm : bpr_alias<"brlz", BPLZnapt, BPLZapt >;
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+defm : bpr_alias<"brnz", BPNZnapt, BPNZapt >;
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+defm : bpr_alias<"brgz", BPGZnapt, BPGZapt >;
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+defm : bpr_alias<"brgez", BPGEZnapt, BPGEZapt>;
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+
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+// Move integer register on register condition (MOVr).
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+multiclass MOVR< bits<3> rcond, string OpcStr> {
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+ def rr : F4_4r<0b101111, 0b00000, rcond, (outs I64Regs:$rd),
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+ (ins I64Regs:$rs1, IntRegs:$rs2),
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+ !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
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+
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+ def ri : F4_4i<0b101111, rcond, (outs I64Regs:$rd),
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+ (ins I64Regs:$rs1, i64imm:$simm10),
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+ !strconcat(OpcStr, " $rs1, $simm10, $rd"), []>;
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+}
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+
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+defm MOVRRZ : MOVR<0b001, "movrz">;
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+defm MOVRLEZ : MOVR<0b010, "movrlez">;
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+defm MOVRLZ : MOVR<0b011, "movrlz">;
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+defm MOVRNZ : MOVR<0b101, "movrnz">;
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+defm MOVRGZ : MOVR<0b110, "movrgz">;
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+defm MOVRGEZ : MOVR<0b111, "movrgez">;
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+
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+// Move FP register on integer register condition (FMOVr).
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+multiclass FMOVR<bits<3> rcond, string OpcStr> {
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+
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+ def S : F4_4r<0b110101, 0b00101, rcond,
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+ (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
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+ !strconcat(!strconcat("fmovrs", OpcStr)," $rs1, $rs2, $rd"),
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+ []>;
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+ def D : F4_4r<0b110101, 0b00110, rcond,
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+ (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
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+ !strconcat(!strconcat("fmovrd", OpcStr)," $rs1, $rs2, $rd"),
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+ []>;
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+ def Q : F4_4r<0b110101, 0b00111, rcond,
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+ (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
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+ !strconcat(!strconcat("fmovrq", OpcStr)," $rs1, $rs2, $rd"),
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+ []>, Requires<[HasHardQuad]>;
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+}
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+
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+let Predicates = [HasV9] in {
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+ defm FMOVRZ : FMOVR<0b001, "z">;
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+ defm FMOVRLEZ : FMOVR<0b010, "lez">;
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+ defm FMOVRLZ : FMOVR<0b011, "lz">;
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+ defm FMOVRNZ : FMOVR<0b101, "nz">;
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+ defm FMOVRGZ : FMOVR<0b110, "gz">;
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+ defm FMOVRGEZ : FMOVR<0b111, "gez">;
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+}
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+
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//===----------------------------------------------------------------------===//
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// 64-bit Floating Point Conversions.
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//===----------------------------------------------------------------------===//
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@@ -470,6 +541,9 @@ def ATOMIC_SWAP_64 : Pseudo<(outs I64Regs:$rd),
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(ins ptr_rc:$addr, I64Regs:$rs2), "",
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[(set i64:$rd,
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(atomic_swap_64 iPTR:$addr, i64:$rs2))]>;
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+
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+let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in
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+ defm TXCC : TRAP<"%xcc">;
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// Global addresses, constant pool entries
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let Predicates = [Is64Bit] in {
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