5508a97976
3.5 snapshot (which around 60% of them did).. r203025, r203050, r203054, r203281, r203581, r203719, r203818, r204155, r204304, r205067, r205630, r205738, r207990, r208501. ok matthew@
41 lines
1.8 KiB
Plaintext
41 lines
1.8 KiB
Plaintext
$OpenBSD: patch-lib_Target_ARM_A15SDOptimizer_cpp,v 1.1 2014/07/10 22:46:37 brad Exp $
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r204304
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Fix an assertion failure in A15SDOptimizer about DPair reg class by treating DPair as QPR.
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--- lib/Target/ARM/A15SDOptimizer.cpp.orig Sun Mar 2 21:57:40 2014
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+++ lib/Target/ARM/A15SDOptimizer.cpp Sat Jun 14 04:09:54 2014
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@@ -416,7 +416,8 @@ SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(M
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if (!MO.isReg() || !MO.isUse())
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continue;
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if (!usesRegClass(MO, &ARM::DPRRegClass) &&
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- !usesRegClass(MO, &ARM::QPRRegClass))
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+ !usesRegClass(MO, &ARM::QPRRegClass) &&
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+ !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
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continue;
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Defs.push_back(MO.getReg());
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@@ -536,7 +537,10 @@ A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *
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InsertPt++;
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unsigned Out;
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- if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) {
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+ // DPair has the same length as QPR and also has two DPRs as subreg.
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+ // Treat DPair as QPR.
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+ if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
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+ MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
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unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
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ARM::dsub_0, &ARM::DPRRegClass);
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unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
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@@ -569,7 +573,9 @@ A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *
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default: llvm_unreachable("Unknown preferred lane!");
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}
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- bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass);
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+ // Treat DPair as QPR
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+ bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
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+ usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
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Out = createImplicitDef(MBB, InsertPt, DL);
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Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
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