45 lines
2.0 KiB
Plaintext
45 lines
2.0 KiB
Plaintext
$OpenBSD: patch-lib_Target_Sparc_SparcInstr64Bit_td,v 1.8 2020/08/05 06:49:48 jca Exp $
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Make sure that we really don't emit quad-precision unless the
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"hard-quad-float" feature is available.
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Index: lib/Target/Sparc/SparcInstr64Bit.td
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--- lib/Target/Sparc/SparcInstr64Bit.td.orig
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+++ lib/Target/Sparc/SparcInstr64Bit.td
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@@ -336,6 +336,7 @@ def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs
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"fmovd$cond %xcc, $rs2, $rd",
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[(set f64:$rd,
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(SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;
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+let Predicates = [Is64Bit, HasHardQuad] in
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def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
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(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
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"fmovq$cond %xcc, $rs2, $rd",
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@@ -436,11 +437,11 @@ def FXTOD : F3_3u<2, 0b110100, 0b010001000,
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(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
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"fxtod $rs2, $rd",
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[(set DFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
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+let Predicates = [Is64Bit, HasHardQuad] in
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def FXTOQ : F3_3u<2, 0b110100, 0b010001100,
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(outs QFPRegs:$rd), (ins DFPRegs:$rs2),
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"fxtoq $rs2, $rd",
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- [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>,
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- Requires<[HasHardQuad]>;
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+ [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
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def FSTOX : F3_3u<2, 0b110100, 0b010000001,
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(outs DFPRegs:$rd), (ins FPRegs:$rs2),
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@@ -450,11 +451,11 @@ def FDTOX : F3_3u<2, 0b110100, 0b010000010,
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(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
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"fdtox $rs2, $rd",
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[(set DFPRegs:$rd, (SPftox DFPRegs:$rs2))]>;
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+let Predicates = [Is64Bit, HasHardQuad] in
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def FQTOX : F3_3u<2, 0b110100, 0b010000011,
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(outs DFPRegs:$rd), (ins QFPRegs:$rs2),
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"fqtox $rs2, $rd",
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- [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>,
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- Requires<[HasHardQuad]>;
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+ [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>;
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} // Predicates = [Is64Bit]
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