000ea76f1f
OK sthen@, port from Alessandro De Laurenzis Comment: full end-to-end digital synthesis flow for VLSI ASIC designs Description: A digital synthesis flow is a set of tools and methods used to turn a VLSI design written in a high-level behavioral language like Verilog or VHDL into a physical circuit, which can either be configuration code for an FPGA target or a layout in a specific technology, that would become part of an IC. Qflow uses a complete and open source tool chain for synthesizing digital circuits starting from Verilog source and ending in physical layout for a specific target fabrication process. Maintainer: Alessandro De Laurenzis WWW: http://opencircuitdesign.com/qflow/
3 lines
106 B
Plaintext
3 lines
106 B
Plaintext
SHA256 (qflow-1.4.83.tgz) = KsBpNmeBjfvucWNoqhGqk6xly1Z+16JEg7NoOpOY1RY=
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SIZE (qflow-1.4.83.tgz) = 952709
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