LibreCAD is a cross-platform 2D CAD program written in C++11 using the Qt
framework. It can read DXF and DWG files and can write DXF, PDF and SVG files.
The user interface is highly customizable, and has dozens of translations.
ok bentley@
timing.c:103:8: warning: incompatible pointer types passing 'long *' to
parameter of type 'time_t *' (aka 'long long *') [-Wincompatible-pointer-types]
Tested by Alessandro DE LAURENZIS (maintainer)
Follow the upstream recommendations for packagers and switch to
multi-packages:
devel/gettext -> devel/gettext,-runtime
devel/gettext-tools -> devel/gettext,-tools
(new) devel/gettext,-textstyle
Qucs-S is a spin-off of the Qucs cross-platform circuit simulator (which
uses its own simulation kernel Qucsator). "S" letter indicates SPICE.
The purpose of the Qucs-S subproject is to use free SPICE circuit
simulation kernels with the Qucs GUI.
Qucs-S is not a simulator by itself, but it requires to use a simulation
backend (Ngspice is recommended).
From Alessandro De Laurenzis; thanks!
ok sthen@
OpenSTA is a gate level static timing verifier. As a stand-alone
executable it can be used to verify the timing of a design using
standard file formats:
- Verilog netlist
- Liberty library
- SDC timing constraints
- SDF delay annotation
- SPEF parasitics
From Alessandro De Laurenzis; thanks!
ok sthen@
Netgen is a tool for comparing netlists, a process known as LVS (Layout
vs. Schematic). This is an important step in the VLSI IC design flow,
ensuring that the geometry that has been laid out matches the expected
circuit.
Netgen is considered complete and competitive with commercial-grade
tools. Code was added to handle device properties and to resolve
parallel combinations of devices whether individually instantiated
or implied through the use of the "M" property. Serial and parallel
networks of passive devices are analyzed and compared between networks.
From Alessandro De Laurenzis; thanks!
ok sthen@
Magic is an interactive system for creating and modifying VLSI
circuit layouts. It is used to design basic cells and to combine
them hierarchically into large structures.
Magic understands quite a bit about the nature of circuits. It has
built-in knowledge of layout rules; during editing, it continuously
checks for rule violations. Magic also knows about connectivity and
transistors, and contains a built-in hierarchical circuit extractor.
It has a plow operation that permits to stretch or compact cells.
Lastly, Magic has routing tools to make the circuit interconnections.
Magic is based on the Mead-Conway style of design: it uses simplified
design rules and circuit structures that make it easier layout drawing
and permit Magic to provide powerful assistance, at the cost of
slightly less dense circuits.
From Alessandro De Laurenzis; thanks!
ok sthen@
Xschem is a schematic capture program, it allows creation of
hierarchical representation of circuits with a top down approach. By
focusing on interfaces, hierarchy and instance properties a complex
system can be described in terms of simpler building blocks.
A VHDL or Verilog or Spice netlist can be generated from the drawn
schematic, allowing the simulation of the circuit. Key feature of the
program is its drawing engine written in C and using directly the Xlib
drawing primitives; this gives very good speed performance, even on
very big circuits. The user interface is built with the Tcl-Tk
toolkit, tcl is also the extension language used.
Netlist can be exported in tEDAx format which can then be used by
pcb-rnd to design a printed circuit board.
From Hannu Vuolasaho <vuokkosetae [at] gmail.com> who takes mainainer.
Feedback from me, OK rsadowski
