Original submission by Alessandro De Laurenzis, who takes MAINTAINER --
thanks!
tweaks and oks from sthen@ and bentley@
graywolf is a program for placement of VLSI digital circuits, mainly
intended as part of qflow tool-chain
(http://opencircuitdesign.com/qflow/).
It is a fork of the last open-source version of TimberWolf (which is now
commercial software) and has been modified to streamline the build
process and make it behave more as a standard command-line tool.
It is based on the general combinatorial optimization technique known as
simulated annealing and is suitable for standard cell, macro/custom
cell, and gate-array professional-grade placement.
design.
Original submission from Alessandro De Laurenzis, who takes MAINTAINER --
thanks!
ok bentley@
Qrouter is a tool to generate metal layers and vias to physically
connect together a netlist in a VLSI fabrication technology. It
is a maze router, otherwise known as an "over-the-cell" router or
"sea-of-gates" router. That is, unlike a channel router, it begins with
a description of placed standard cells, usually packed together at
minimum spacing, and places metal routes over the standard cells.
Qrouter uses the open standard LEF and DEF formats as file input and
output. It takes the cell definitions from a LEF file, and analyzes
the geometry for each cell to determine contact points and route
obstructions. It then reads the cell placement, pin placement, and
netlist from a DEF file, performs the detailed route, and writes an
annotated DEF file as output.
Yosys Open SYnthesis Suite
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains. Selected features and typical applications:
- Process almost any synthesizable Verilog-2005 design
- Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
- Built-in formal methods for checking properties and equivalence
- Mapping to ASIC standard cell libraries (in Liberty File Format)
- Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
- Foundation and/or front-end for custom flows
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the Yosys C++ code base.
Original submission from Alessandro De Laurenzis, who takes MAINTAINER --
thanks!
Additional work from sthen@ and myself, ok sthen@
ABC is a growing software system for synthesis and verification of binary
sequential logic circuits appearing in synchronous hardware designs. ABC
combines scalable logic optimization based on And-Inverter Graphs (AIGs),
optimal-delay DAG-based technology mapping for look-up tables and standard
cells, and innovative algorithms for sequential synthesis and verification.
