Commit Graph

6 Commits

Author SHA1 Message Date
sthen
10a4eaad69 update to abc-1.01.20210519, from maintainer 2021-05-23 13:04:01 +00:00
sthen
20498cf97d add a comment explaining pre-configure 2020-01-16 22:33:54 +00:00
sthen
90b4880dbf update to newer cad/abc checkout, from maintainer Alessandro De Laurenzis 2020-01-16 22:32:48 +00:00
sthen
9fe1e38b23 replace simple PERMIT_PACKAGE_CDROM=Yes with PERMIT_PACKAGE=Yes 2019-07-12 20:43:27 +00:00
sthen
25f0e460f2 Add COMPILER lines to c++ ports which currently use the default. Adjust
some existing COMPILER lines with arch restrictions etc. In the usual
case this is now using "COMPILER = base-clang ports-gcc base-gcc" on
ports with c++ libraries in WANTLIB.

This is basically intended to be a noop on architectures using clang
as the system compiler, but help with other architectures where we
currently have many ports knocked out due to building with an unsuitable
compiler -

- some ports require c++11/newer so the GCC version in base that is used
on these archirtectures is too old.

- some ports have conflicts where an executable is built with one compiler
(e.g. gcc from base) but a library dependency is built with a different
one (e.g. gcc from ports), resulted in mixing incompatible libraries in the
same address space.

devel/gmp is intentionally skipped as it's on the path to building gcc -
the c++ library there is unused in ports (and not built by default upstream)
so intending to disable building gmpcxx in a future commit.
2018-10-24 14:27:57 +00:00
bcallah
f919501846 Import cad/abc, a system for sequential logic synthesis and verification.
Original submission from Alessandro De Laurenzis, who takes MAINTAINER --
thanks!

Additional work from sthen@ and myself, ok sthen@

ABC is a growing software system for synthesis and verification of binary
sequential logic circuits appearing in synchronous hardware designs. ABC
combines scalable logic optimization based on And-Inverter Graphs (AIGs),
optimal-delay DAG-based technology mapping for look-up tables and standard
cells, and innovative algorithms for sequential synthesis and verification.
2018-08-08 15:24:47 +00:00