as MODTK_WANTLIB already includes it).
OCE is a C++ 3D modeling library. It can be used to develop CAD/CAM softwares,
for instance FreeCad or IfcOpenShell.
OCE stands for opencascade community edition. This project aims at gathering
patches/ changes/ improvements from the OCC community. Official OCCT
documentation and sources are available at http://www.opencascade.org/, you can
also check their development portal at http://dev.opencascade.org.
While here:
- Switch to HTTPS
- Regen WANTLIB
- Remove math/double-conversion from BUILD_DEPENDS because it's in
LIB_DEPENDS.
- Remove base-gcc from COMPILER. We need a C++11 compiler to build
openscad
LibreCAD is a cross-platform 2D CAD program written in C++11 using the Qt
framework. It can read DXF and DWG files and can write DXF, PDF and SVG files.
The user interface is highly customizable, and has dozens of translations.
ok bentley@
timing.c:103:8: warning: incompatible pointer types passing 'long *' to
parameter of type 'time_t *' (aka 'long long *') [-Wincompatible-pointer-types]
Tested by Alessandro DE LAURENZIS (maintainer)
Follow the upstream recommendations for packagers and switch to
multi-packages:
devel/gettext -> devel/gettext,-runtime
devel/gettext-tools -> devel/gettext,-tools
(new) devel/gettext,-textstyle
Qucs-S is a spin-off of the Qucs cross-platform circuit simulator (which
uses its own simulation kernel Qucsator). "S" letter indicates SPICE.
The purpose of the Qucs-S subproject is to use free SPICE circuit
simulation kernels with the Qucs GUI.
Qucs-S is not a simulator by itself, but it requires to use a simulation
backend (Ngspice is recommended).
From Alessandro De Laurenzis; thanks!
ok sthen@
OpenSTA is a gate level static timing verifier. As a stand-alone
executable it can be used to verify the timing of a design using
standard file formats:
- Verilog netlist
- Liberty library
- SDC timing constraints
- SDF delay annotation
- SPEF parasitics
From Alessandro De Laurenzis; thanks!
ok sthen@
Netgen is a tool for comparing netlists, a process known as LVS (Layout
vs. Schematic). This is an important step in the VLSI IC design flow,
ensuring that the geometry that has been laid out matches the expected
circuit.
Netgen is considered complete and competitive with commercial-grade
tools. Code was added to handle device properties and to resolve
parallel combinations of devices whether individually instantiated
or implied through the use of the "M" property. Serial and parallel
networks of passive devices are analyzed and compared between networks.
From Alessandro De Laurenzis; thanks!
ok sthen@
