"This is a trivial update port-wise, but a big jump in terms of
features/bug-fixing."
Notable port changes:
- updated maintainer email address;
- ApiChanges.txt added to ${PREFIX}/share/doc/opensta;
- new enabled regression suite
Diff from maintainer Alessandro De Laurenzis
OpenSTA is a gate level static timing verifier. As a stand-alone
executable it can be used to verify the timing of a design using
standard file formats:
- Verilog netlist
- Liberty library
- SDC timing constraints
- SDF delay annotation
- SPEF parasitics
From Alessandro De Laurenzis; thanks!
ok sthen@
naddy
sthen
rsadowski
bentley