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import port/devel/xtensa-esp32s3-elf, ok sthen@

Browse Source 
The xtensa-esp32s3-elf port is an ESP32 GNU cross compiler suite, configured for
the xtensa-esp32s3-elf target.

ESP32-S3 is a dual-core XTensa LX7 MCU, capable of running at 240 MHz. Apart
from its 512 KB of internal SRAM, it also comes with integrated 2.4 GHz, 802.11
b/g/n Wi-Fi and Bluetooth 5 (LE) connectivity that provides long-range support.
It has 45 programmable GPIOs and supports a rich set of peripherals. ESP32-S3
supports larger, high-speed octal SPI flash, and PSRAM with configurable data
and instruction cache.
This commit is contained in:
tracey 2022-06-27 10:05:25 +00:00
parent d7b8c70656
commit a1374e7146
35 changed files with 81178 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
devel/xtensa-esp32s3-elf/Makefile Normal file
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@ -0,0 +1,8 @@
SUBDIR =
SUBDIR += binutils
SUBDIR += gcc-bootstrap
SUBDIR += newlib
SUBDIR += gcc
SUBDIR += gdb
.include <bsd.port.subdir.mk>

50
devel/xtensa-esp32s3-elf/Makefile.inc Normal file
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@ -0,0 +1,50 @@
CONFIG = xtensa-esp32s3-elf
CATEGORIES += devel
HOMEPAGE = https://www.espressif.com/en/products/software/esp-sdk/overview
# DEBUG_PACKAGES = ${BUILD_PACKAGES}
# GPLv3
# For newlib: multiple copyrights, but basically BSD.
# See: ${PREFIX}/share/doc/newlib
PERMIT_PACKAGE = Yes
# permits build on sparc64
COMPILER = base-clang ports-clang
BUILD_DEPENDS += devel/bison \
lang/gawk \
sysutils/coreutils \
textproc/gsed
SEPARATE_BUILD = Yes
USE_GMAKE = Yes
YACC = bison -y
CE_VARS = "-mlongcalls -Os -g -free -fipa-pta"
INSTALLDIR = "${LOCALBASE}/${CONFIG}"
CONFIGURE_STYLE ?= simple
CONFIGURE_ENV += CFLAGS_FOR_TARGET=${CE_VARS} \
CXXFLAGS_FOR_TARGET=${CE_VARS} \
CFLAGS="-I${INSTALLDIR}/include -pipe -g" \
LDFLAGS="-L${INSTALLDIR}/lib -g"
CONFIGURE_ARGS += --target="${CONFIG}" \
--prefix="${INSTALLDIR}" \
--disable-shared \
--with-newlib \
--enable-threads=no \
--disable-__cxa_atexit \
--disable-libgomp \
--disable-libmudflap \
--disable-nls \
--disable-bootstrap \
--enable-languages=c,c++ \
--disable-lto \
--disable-libstdcxx-verbose \
--disable-option-checking \
--without-long-double-128 \
--with-system-zlib \
--enable-static=yes
NO_TEST = Yes

17
devel/xtensa-esp32s3-elf/binutils/Makefile Normal file
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@ -0,0 +1,17 @@
COMMENT = binutils for ${CONFIG} cross-development
VERSION = 2.35.1.2020.1223
PKGNAME = ${CONFIG}-binutils-${VERSION}
GH_ACCOUNT = espressif
GH_PROJECT = binutils-gdb
GH_TAGNAME = esp-2021r2-binutils
WANTLIB += c z
CONFIGURE_ARGS += --disable-multilib \
--with-gnu-as \
--with-gnu-ld \
--disable-werror \
--disable-gdb
.include <bsd.port.mk>

2
devel/xtensa-esp32s3-elf/binutils/distinfo Normal file
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@ -0,0 +1,2 @@
SHA256 (binutils-gdb-esp-2021r2-binutils.tar.gz) = zsRv11iRKXZVSpMDVfg6iTkt4YO1nXXXRbj9qwFzDIk=
SIZE (binutils-gdb-esp-2021r2-binutils.tar.gz) = 60652952

26976
devel/xtensa-esp32s3-elf/binutils/patches/patch-bfd_xtensa-modules_c Normal file
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File diff suppressed because it is too large Load Diff

144
devel/xtensa-esp32s3-elf/binutils/patches/patch-include_xtensa-config_h Normal file
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@ -0,0 +1,144 @@
Index: include/xtensa-config.h
--- include/xtensa-config.h.orig
+++ include/xtensa-config.h
@@ -1,5 +1,6 @@
/* Xtensa configuration settings.
- Copyright (C) 2001-2020 Free Software Foundation, Inc.
+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+ Free Software Foundation, Inc.
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
This program is free software; you can redistribute it and/or modify
@@ -25,7 +26,7 @@
macros. */
#undef XCHAL_HAVE_BE
-#define XCHAL_HAVE_BE 1
+#define XCHAL_HAVE_BE 0
#undef XCHAL_HAVE_DENSITY
#define XCHAL_HAVE_DENSITY 1
@@ -49,7 +50,7 @@
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#undef XCHAL_HAVE_MAC16
-#define XCHAL_HAVE_MAC16 0
+#define XCHAL_HAVE_MAC16 1
#undef XCHAL_HAVE_MUL16
#define XCHAL_HAVE_MUL16 1
@@ -58,7 +59,7 @@
#define XCHAL_HAVE_MUL32 1
#undef XCHAL_HAVE_MUL32_HIGH
-#define XCHAL_HAVE_MUL32_HIGH 0
+#define XCHAL_HAVE_MUL32_HIGH 1
#undef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 1
@@ -85,30 +86,37 @@
#define XCHAL_HAVE_S32C1I 1
#undef XCHAL_HAVE_BOOLEANS
-#define XCHAL_HAVE_BOOLEANS 0
+#define XCHAL_HAVE_BOOLEANS 1
#undef XCHAL_HAVE_FP
-#define XCHAL_HAVE_FP 0
+#define XCHAL_HAVE_FP 1
#undef XCHAL_HAVE_FP_DIV
-#define XCHAL_HAVE_FP_DIV 0
+#define XCHAL_HAVE_FP_DIV 1
#undef XCHAL_HAVE_FP_RECIP
-#define XCHAL_HAVE_FP_RECIP 0
+#define XCHAL_HAVE_FP_RECIP 1
#undef XCHAL_HAVE_FP_SQRT
-#define XCHAL_HAVE_FP_SQRT 0
+#define XCHAL_HAVE_FP_SQRT 1
#undef XCHAL_HAVE_FP_RSQRT
-#define XCHAL_HAVE_FP_RSQRT 0
+#define XCHAL_HAVE_FP_RSQRT 1
+#undef XCHAL_HAVE_FP_POSTINC
+#define XCHAL_HAVE_FP_POSTINC 1
+
+#undef XCHAL_HAVE_DFP_ACCEL
+#define XCHAL_HAVE_DFP_ACCEL 1
+/* For backward compatibility */
#undef XCHAL_HAVE_DFP_accel
-#define XCHAL_HAVE_DFP_accel 0
+#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
+
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
#undef XCHAL_NUM_AREGS
-#define XCHAL_NUM_AREGS 32
+#define XCHAL_NUM_AREGS 64
#undef XCHAL_HAVE_WIDE_BRANCHES
#define XCHAL_HAVE_WIDE_BRANCHES 0
@@ -118,34 +126,31 @@
#undef XCHAL_ICACHE_SIZE
-#define XCHAL_ICACHE_SIZE 16384
+#define XCHAL_ICACHE_SIZE 0
#undef XCHAL_DCACHE_SIZE
-#define XCHAL_DCACHE_SIZE 16384
+#define XCHAL_DCACHE_SIZE 0
#undef XCHAL_ICACHE_LINESIZE
-#define XCHAL_ICACHE_LINESIZE 32
+#define XCHAL_ICACHE_LINESIZE 16
#undef XCHAL_DCACHE_LINESIZE
-#define XCHAL_DCACHE_LINESIZE 32
+#define XCHAL_DCACHE_LINESIZE 16
#undef XCHAL_ICACHE_LINEWIDTH
-#define XCHAL_ICACHE_LINEWIDTH 5
+#define XCHAL_ICACHE_LINEWIDTH 4
#undef XCHAL_DCACHE_LINEWIDTH
-#define XCHAL_DCACHE_LINEWIDTH 5
+#define XCHAL_DCACHE_LINEWIDTH 4
#undef XCHAL_DCACHE_IS_WRITEBACK
-#define XCHAL_DCACHE_IS_WRITEBACK 1
+#define XCHAL_DCACHE_IS_WRITEBACK 0
#undef XCHAL_HAVE_MMU
-#define XCHAL_HAVE_MMU 1
+#define XCHAL_HAVE_MMU 0
-#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
-
#undef XCHAL_HAVE_DEBUG
#define XCHAL_HAVE_DEBUG 1
@@ -172,5 +177,16 @@
#define XSHAL_ABI XTHAL_ABI_WINDOWED
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
+
+
+#undef XCHAL_M_STAGE
+#define XCHAL_M_STAGE 3
+
+#undef XTENSA_MARCH_LATEST
+#define XTENSA_MARCH_LATEST 260003
+
+#undef XTENSA_MARCH_EARLIEST
+#define XTENSA_MARCH_EARLIEST 260003
+
#endif /* !XTENSA_CONFIG_H */

24
devel/xtensa-esp32s3-elf/binutils/pkg/DESCR Normal file
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@ -0,0 +1,24 @@
GNU Binutils collection, configured for the xtensa-esp32s3-elf target.
* ld - the GNU linker.
* as - the GNU assembler.
But they also include:
* addr2line - Converts addresses into filenames and line numbers.
* ar - A utility for creating, modifying and extracting from
archives.
* c++filt - Filter to demangle encoded C++ symbols.
* gprof - Displays profiling information.
* nlmconv - Converts object code into an NLM.
* nm - Lists symbols from object files.
* objcopy - Copys and translates object files.
* objdump - Displays information from object files.
* ranlib - Generates an index to the contents of an archive.
* readelf - Displays information from any ELF format object file.
* size - Lists the section sizes of an object or archive file.
* strings - Lists printable strings from files.
* strip - Discards symbols.
* windres - A compiler for Windows resource files.
Most of these programs use BFD, the Binary File Descriptor library, to
do low-level manipulation. Many of them also use the opcodes library
to assemble and disassemble machine instructions.

81
devel/xtensa-esp32s3-elf/binutils/pkg/PLIST Normal file
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@ -0,0 +1,81 @@
xtensa-esp32s3-elf/
xtensa-esp32s3-elf/bin/
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-addr2line
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-ar
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-as
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-c++filt
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-elfedit
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-gprof
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-ld
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-ld.bfd
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-nm
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-objcopy
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-objdump
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-ranlib
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-readelf
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-size
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-strings
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-strip
xtensa-esp32s3-elf/lib/
xtensa-esp32s3-elf/lib/ldscripts/
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.x
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xbn
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xc
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xce
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xd
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xdc
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xdce
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xde
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xdw
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xdwe
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xe
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xn
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xr
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xs
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xsc
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xsce
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xse
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xsw
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xswe
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xu
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xw
xtensa-esp32s3-elf/lib/ldscripts/elf32xtensa.xwe
xtensa-esp32s3-elf/share/
@info xtensa-esp32s3-elf/share/info/
@info xtensa-esp32s3-elf/share/info/as.info
@info xtensa-esp32s3-elf/share/info/bfd.info
@info xtensa-esp32s3-elf/share/info/binutils.info
@info xtensa-esp32s3-elf/share/info/gprof.info
@info xtensa-esp32s3-elf/share/info/ld.info
@mandir xtensa-esp32s3-elf/share/man/
xtensa-esp32s3-elf/share/man/man1/
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-addr2line.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-ar.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-as.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-c++filt.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-dlltool.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-elfedit.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-gprof.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-ld.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-nm.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-objcopy.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-objdump.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-ranlib.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-readelf.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-size.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-strings.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-strip.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-windmc.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-windres.1
xtensa-esp32s3-elf/xtensa-esp32s3-elf/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/bin/
@bin xtensa-esp32s3-elf/xtensa-esp32s3-elf/bin/ar
@bin xtensa-esp32s3-elf/xtensa-esp32s3-elf/bin/as
@bin xtensa-esp32s3-elf/xtensa-esp32s3-elf/bin/ld
@bin xtensa-esp32s3-elf/xtensa-esp32s3-elf/bin/ld.bfd
@bin xtensa-esp32s3-elf/xtensa-esp32s3-elf/bin/nm
@bin xtensa-esp32s3-elf/xtensa-esp32s3-elf/bin/objcopy
@bin xtensa-esp32s3-elf/xtensa-esp32s3-elf/bin/objdump
@bin xtensa-esp32s3-elf/xtensa-esp32s3-elf/bin/ranlib
@bin xtensa-esp32s3-elf/xtensa-esp32s3-elf/bin/readelf
@bin xtensa-esp32s3-elf/xtensa-esp32s3-elf/bin/strip

38
devel/xtensa-esp32s3-elf/gcc-bootstrap/Makefile Normal file
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@ -0,0 +1,38 @@
COMMENT = bootstrap compiler for ${CONFIG} cross-development
V = 8.4.0
VERSION = ${V}.2021.2
PKGNAME = ${CONFIG}-gcc-bootstrap-${VERSION}
GH_ACCOUNT = espressif
GH_PROJECT = gcc
GH_TAGNAME = esp-2021r2
WANTLIB = ${COMPILER_LIBCXX} c gmp isl m mpc mpfr z
SUBST_VARS += V
.if ${MACHINE_ARCH} == "powerpc64"
PATCH_LIST = patch-* vecstep-*
.endif
BUILD_DEPENDS += devel/${CONFIG}/binutils
LIB_DEPENDS = devel/gmp \
devel/mpfr \
devel/libmpc \
math/isl
CONFIGURE_ARGS += --exec-prefix="${INSTALLDIR}/bootstrap" \
--with-as="${INSTALLDIR}/bin/${CONFIG}-as" \
--with-ld="${INSTALLDIR}/bin/${CONFIG}-ld" \
--with-gmp="${LOCALBASE}" \
--with-isl="${LOCALBASE}"
ALL_TARGET = all-gcc
INSTALL_TARGET = install-gcc
post-install:
chown -R ${SHAREOWN}:${SHAREGRP} \
${PREFIX}/${CONFIG}/lib/gcc/${CONFIG}/${VERSION}/
.include <bsd.port.mk>

2
devel/xtensa-esp32s3-elf/gcc-bootstrap/distinfo Normal file
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@ -0,0 +1,2 @@
SHA256 (gcc-esp-2021r2.tar.gz) = lJ1lgKB6lUmO2/DDU36oQNgDVk2HT995EnX17MlksJs=
SIZE (gcc-esp-2021r2.tar.gz) = 102863056

155
devel/xtensa-esp32s3-elf/gcc-bootstrap/patches/patch-include_xtensa-config_h Normal file
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@ -0,0 +1,155 @@
xtensa-config.h for ESP32
Index: include/xtensa-config.h
--- include/xtensa-config.h.orig
+++ include/xtensa-config.h
@@ -1,5 +1,6 @@
/* Xtensa configuration settings.
- Copyright (C) 2001-2018 Free Software Foundation, Inc.
+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+ Free Software Foundation, Inc.
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
This program is free software; you can redistribute it and/or modify
@@ -25,7 +26,7 @@
macros. */
#undef XCHAL_HAVE_BE
-#define XCHAL_HAVE_BE 1
+#define XCHAL_HAVE_BE 0
#undef XCHAL_HAVE_DENSITY
#define XCHAL_HAVE_DENSITY 1
@@ -49,7 +50,7 @@
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#undef XCHAL_HAVE_MAC16
-#define XCHAL_HAVE_MAC16 0
+#define XCHAL_HAVE_MAC16 1
#undef XCHAL_HAVE_MUL16
#define XCHAL_HAVE_MUL16 1
@@ -58,7 +59,7 @@
#define XCHAL_HAVE_MUL32 1
#undef XCHAL_HAVE_MUL32_HIGH
-#define XCHAL_HAVE_MUL32_HIGH 0
+#define XCHAL_HAVE_MUL32_HIGH 1
#undef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 1
@@ -85,30 +86,37 @@
#define XCHAL_HAVE_S32C1I 1
#undef XCHAL_HAVE_BOOLEANS
-#define XCHAL_HAVE_BOOLEANS 0
+#define XCHAL_HAVE_BOOLEANS 1
#undef XCHAL_HAVE_FP
-#define XCHAL_HAVE_FP 0
+#define XCHAL_HAVE_FP 1
#undef XCHAL_HAVE_FP_DIV
-#define XCHAL_HAVE_FP_DIV 0
+#define XCHAL_HAVE_FP_DIV 1
#undef XCHAL_HAVE_FP_RECIP
-#define XCHAL_HAVE_FP_RECIP 0
+#define XCHAL_HAVE_FP_RECIP 1
#undef XCHAL_HAVE_FP_SQRT
-#define XCHAL_HAVE_FP_SQRT 0
+#define XCHAL_HAVE_FP_SQRT 1
#undef XCHAL_HAVE_FP_RSQRT
-#define XCHAL_HAVE_FP_RSQRT 0
+#define XCHAL_HAVE_FP_RSQRT 1
+#undef XCHAL_HAVE_FP_POSTINC
+#define XCHAL_HAVE_FP_POSTINC 1
+
+#undef XCHAL_HAVE_DFP_ACCEL
+#define XCHAL_HAVE_DFP_ACCEL 0
+/* For backward compatibility */
#undef XCHAL_HAVE_DFP_accel
-#define XCHAL_HAVE_DFP_accel 0
+#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
+
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
#undef XCHAL_NUM_AREGS
-#define XCHAL_NUM_AREGS 32
+#define XCHAL_NUM_AREGS 64
#undef XCHAL_HAVE_WIDE_BRANCHES
#define XCHAL_HAVE_WIDE_BRANCHES 0
@@ -118,34 +126,31 @@
#undef XCHAL_ICACHE_SIZE
-#define XCHAL_ICACHE_SIZE 16384
+#define XCHAL_ICACHE_SIZE 0
#undef XCHAL_DCACHE_SIZE
-#define XCHAL_DCACHE_SIZE 16384
+#define XCHAL_DCACHE_SIZE 0
#undef XCHAL_ICACHE_LINESIZE
-#define XCHAL_ICACHE_LINESIZE 32
+#define XCHAL_ICACHE_LINESIZE 16
#undef XCHAL_DCACHE_LINESIZE
-#define XCHAL_DCACHE_LINESIZE 32
+#define XCHAL_DCACHE_LINESIZE 16
#undef XCHAL_ICACHE_LINEWIDTH
-#define XCHAL_ICACHE_LINEWIDTH 5
+#define XCHAL_ICACHE_LINEWIDTH 4
#undef XCHAL_DCACHE_LINEWIDTH
-#define XCHAL_DCACHE_LINEWIDTH 5
+#define XCHAL_DCACHE_LINEWIDTH 4
#undef XCHAL_DCACHE_IS_WRITEBACK
-#define XCHAL_DCACHE_IS_WRITEBACK 1
+#define XCHAL_DCACHE_IS_WRITEBACK 0
#undef XCHAL_HAVE_MMU
-#define XCHAL_HAVE_MMU 1
+#define XCHAL_HAVE_MMU 0
-#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
-
#undef XCHAL_HAVE_DEBUG
#define XCHAL_HAVE_DEBUG 1
@@ -160,7 +165,7 @@
#undef XCHAL_MAX_INSTRUCTION_SIZE
-#define XCHAL_MAX_INSTRUCTION_SIZE 3
+#define XCHAL_MAX_INSTRUCTION_SIZE 4
#undef XCHAL_INST_FETCH_WIDTH
#define XCHAL_INST_FETCH_WIDTH 4
@@ -172,5 +177,16 @@
#define XSHAL_ABI XTHAL_ABI_WINDOWED
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
+
+
+#undef XCHAL_M_STAGE
+#define XCHAL_M_STAGE 2
+
+#undef XTENSA_MARCH_LATEST
+#define XTENSA_MARCH_LATEST 270012
+
+#undef XTENSA_MARCH_EARLIEST
+#define XTENSA_MARCH_EARLIEST 270012
+
#endif /* !XTENSA_CONFIG_H */

1
devel/xtensa-esp32s3-elf/gcc-bootstrap/pkg/DESCR Normal file
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@ -0,0 +1 @@
Bootstrap cross compiler configured for the xtensa-esp32s3-elf target.

491
devel/xtensa-esp32s3-elf/gcc-bootstrap/pkg/PLIST Normal file
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@ -0,0 +1,491 @@
xtensa-esp32s3-elf/
xtensa-esp32s3-elf/bootstrap/
xtensa-esp32s3-elf/bootstrap/bin/
@bin xtensa-esp32s3-elf/bootstrap/bin/xtensa-esp32s3-elf-c++
@bin xtensa-esp32s3-elf/bootstrap/bin/xtensa-esp32s3-elf-cpp
@bin xtensa-esp32s3-elf/bootstrap/bin/xtensa-esp32s3-elf-g++
@bin xtensa-esp32s3-elf/bootstrap/bin/xtensa-esp32s3-elf-gcc
@bin xtensa-esp32s3-elf/bootstrap/bin/xtensa-esp32s3-elf-gcc-${V}
@bin xtensa-esp32s3-elf/bootstrap/bin/xtensa-esp32s3-elf-gcc-ar
@bin xtensa-esp32s3-elf/bootstrap/bin/xtensa-esp32s3-elf-gcc-nm
@bin xtensa-esp32s3-elf/bootstrap/bin/xtensa-esp32s3-elf-gcc-ranlib
@bin xtensa-esp32s3-elf/bootstrap/bin/xtensa-esp32s3-elf-gcov
@bin xtensa-esp32s3-elf/bootstrap/bin/xtensa-esp32s3-elf-gcov-dump
@bin xtensa-esp32s3-elf/bootstrap/bin/xtensa-esp32s3-elf-gcov-tool
xtensa-esp32s3-elf/bootstrap/lib/
xtensa-esp32s3-elf/bootstrap/lib/gcc/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include-fixed/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include-fixed/README
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include-fixed/limits.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include-fixed/syslimits.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/float.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/iso646.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/stdalign.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/stdarg.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/stdatomic.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/stdbool.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/stddef.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/stdfix.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/stdint-gcc.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/stdint.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/stdnoreturn.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/tgmath.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/include/varargs.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/install-tools/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/install-tools/fixinc_list
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/install-tools/gsyslimits.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/install-tools/include/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/install-tools/include/README
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/install-tools/include/limits.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/install-tools/macro_list
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/install-tools/mkheaders.conf
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/gtype.state
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/ada/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/ada/gcc-interface/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/ada/gcc-interface/ada-tree.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/addresses.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/alias.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/all-tree.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/alloc-pool.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/ansidecl.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/asan.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/attribs.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/auto-host.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/auto-profile.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/b-header-vars
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/backend.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/basic-block.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/bb-reorder.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/bitmap.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/brig-builtins.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/builtin-attrs.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/builtin-types.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/builtins.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/builtins.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/bversion.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/c-family/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/c-family/c-common.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/c-family/c-common.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/c-family/c-objc.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/c-family/c-pragma.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/c-family/c-pretty-print.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/c-tree.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/calls.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/ccmp.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cfg-flags.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cfg.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cfganal.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cfgbuild.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cfgcleanup.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cfgexpand.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cfghooks.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cfgloop.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cfgloopmanip.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cfgrtl.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cgraph.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/chkp-builtins.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cif-code.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/collect-utils.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/collect2-aix.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/collect2.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/color-macros.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/conditions.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/config/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/config.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/config/dbxelf.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/config/elfos.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/config/initfini-array.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/config/newlib-stdint.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/config/xtensa/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/config/xtensa/elf.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/config/xtensa/xtensa-opts.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/config/xtensa/xtensa-protos.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/config/xtensa/xtensa.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/configargs.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/context.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/convert.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/coretypes.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/coverage.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cp/
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cp/cp-tree.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cp/cp-tree.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cp/cxx-pretty-print.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cp/name-lookup.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cp/operators.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cp/type-utils.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cppbuiltin.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cppdefault.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cpplib.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/cselib.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/data-streamer.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/dbgcnt.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/dbgcnt.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/dbxout.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/dce.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/ddg.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/debug.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/defaults.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/df.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/dfp.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/diagnostic-color.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/diagnostic-core.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/diagnostic.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/diagnostic.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/dojump.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/dominance.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/domwalk.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/double-int.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/dumpfile.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/dwarf2asm.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/dwarf2out.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/edit-context.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/emit-rtl.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/errors.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/et-forest.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/except.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/explow.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/expmed.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/expr.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/fibonacci_heap.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/file-find.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/file-prefix-map.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/filenames.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/fixed-value.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/flag-types.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/flags.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/fold-const-call.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/fold-const.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/function.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gcc-plugin.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gcc-rich-location.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gcc-symtab.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gcc.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gcov-counter.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gcov-io.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gcse-common.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gcse.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/generic-match.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gengtype.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/genrtl.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gensupport.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/ggc-internal.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/ggc.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-builder.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-expr.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-fold.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-iterator.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-low.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-match.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-predict.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-pretty-print.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-ssa-evrp-analyze.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-ssa-warn-restrict.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-ssa.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-streamer.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple-walk.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimple.def
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xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimplify-me.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gimplify.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/glimits.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/graph.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/graphds.h
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xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gsstruct.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gstab.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gsyms.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gsyslimits.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/gtm-builtins.def
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xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/hash-map-traits.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/hash-map.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/hash-set.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/hash-table.h
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xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/hashtab.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/highlev-plugin-common.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/hooks.h
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xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-live.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-loop-ivopts.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-loop-manip.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-loop-niter.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-loop.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-operands.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-propagate.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-sccvn.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-scopedtables.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-strlen.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-ter.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-threadedge.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa-threadupdate.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssa.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-ssanames.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-stdarg.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-streamer.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-vector-builder.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-vectorizer.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree-vrp.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tree.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/treestruct.def
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tsan.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/tsystem.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/typeclass.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/typed-splay-tree.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/ubsan.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/valtrack.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/value-prof.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/varasm.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/vec-perm-indices.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/vec.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/vector-builder.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/version.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/vmsdbg.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/vr-values.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/vtable-verify.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/wide-int-bitmask.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/wide-int-print.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/wide-int.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/xcoff.h
xtensa-esp32s3-elf/bootstrap/lib/gcc/xtensa-esp32s3-elf/${V}/plugin/include/xcoffout.h
xtensa-esp32s3-elf/bootstrap/libexec/
xtensa-esp32s3-elf/bootstrap/libexec/gcc/
xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/
xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/${V}/
@bin xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/${V}/cc1
@bin xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/${V}/cc1plus
@bin xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/${V}/collect2
xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/${V}/install-tools/
xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/${V}/install-tools/fixinc.sh
@bin xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/${V}/install-tools/fixincl
xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/${V}/install-tools/mkheaders
xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/${V}/install-tools/mkinstalldirs
@bin xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/${V}/lto-wrapper
xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/${V}/plugin/
@bin xtensa-esp32s3-elf/bootstrap/libexec/gcc/xtensa-esp32s3-elf/${V}/plugin/gengtype
xtensa-esp32s3-elf/include/
xtensa-esp32s3-elf/share/
@comment @info xtensa-esp32s3-elf/share/info/
@comment @info xtensa-esp32s3-elf/share/info/cpp.info
@comment @info xtensa-esp32s3-elf/share/info/cppinternals.info
@comment @info xtensa-esp32s3-elf/share/info/gcc.info
@comment @info xtensa-esp32s3-elf/share/info/gccinstall.info
@comment @info xtensa-esp32s3-elf/share/info/gccint.info
@comment @mandir xtensa-esp32s3-elf/share/man/
@comment xtensa-esp32s3-elf/share/man/man1/
@comment @man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-cpp.1
@comment @man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-g++.1
@comment @man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-gcc.1
@comment @man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-gcov-dump.1
@comment @man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-gcov-tool.1
@comment @man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-gcov.1
@comment xtensa-esp32s3-elf/share/man/man7/
@comment @man xtensa-esp32s3-elf/share/man/man7/fsf-funding.7
@comment @man xtensa-esp32s3-elf/share/man/man7/gfdl.7
@comment @man xtensa-esp32s3-elf/share/man/man7/gpl.7

59
devel/xtensa-esp32s3-elf/gcc/Makefile Normal file
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@ -0,0 +1,59 @@
COMMENT = gcc for ${CONFIG} cross-development
V = 8.4.0
VERSION = ${V}.2021.2
PKGNAME = ${CONFIG}-gcc-${VERSION}
SHARED_LIBS += cc1plugin 0.0 # 0.0
SHARED_LIBS += cp1plugin 0.0 # 0.0
SHARED_LIBS += cc1 0.0 # 0.0
GH_ACCOUNT = espressif
GH_PROJECT = gcc
GH_TAGNAME = esp-2021r2
WANTLIB = ${COMPILER_LIBCXX} c gmp isl m mpc mpfr z
SUBST_VARS += V
LIBELF = libelf-0.8.13
MASTER_SITES0 = https://github.com/earlephilhower/esp-quick-toolchain/raw/master/blobs/
DISTFILES = ${DISTNAME}${EXTRACT_SUFX}
DISTFILES += ${LIBELF}${EXTRACT_SUFX}:0
.if ${MACHINE_ARCH} == "powerpc64"
PATCH_LIST = patch-* vecstep-*
.endif
MODULES = lang/python
BUILD_DEPENDS += devel/${CONFIG}/binutils \
devel/${CONFIG}/newlib
RUN_DEPENDS = devel/${CONFIG}/binutils \
devel/${CONFIG}/newlib
LIB_DEPENDS = devel/gmp \
devel/libmpc \
devel/mpfr \
math/isl
CONFIGURE_ENV += AR_FOR_TARGET="${INSTALLDIR}/bin/${CONFIG}-ar" \
RANLIB_FOR_TARGET="${INSTALLDIR}/bin/${CONFIG}-ranlib"
CONFIGURE_ARGS += --with-as="${INSTALLDIR}/bin/${CONFIG}-as" \
--with-ld="${INSTALLDIR}/bin/${CONFIG}-ld" \
--with-sysroot="${INSTALLDIR}/${CONFIG}" \
--with-gmp="${LOCALBASE}" \
--with-isl="${LOCALBASE}" \
--enable-target-optspace \
--enable-gcov-custom-rtio \
--enable-libstdcxx-time=yes
post-extract:
mv ${WRKDIR}/${LIBELF} ${WRKSRC}/libelf
post-install:
chown -R ${SHAREOWN}:${SHAREGRP} \
${PREFIX}/lib/gcc/${CONFIG}/${V}/
${MODPY_BIN} ${MODPY_LIBDIR}/compileall.py ${PREFIX}/${CONFIG}/
@cd ${PREFIX}/${CONFIG}/bin && ln -s ${CONFIG}-gcc ${CONFIG}-cc
.include <bsd.port.mk>

4
devel/xtensa-esp32s3-elf/gcc/distinfo Normal file
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@ -0,0 +1,4 @@
SHA256 (gcc-esp-2021r2.tar.gz) = lJ1lgKB6lUmO2/DDU36oQNgDVk2HT995EnX17MlksJs=
SHA256 (libelf-0.8.13.tar.gz) = WRqbTsgcHyBCqXqmBWTgy3nQQcUvqnQWrLOLyVvSx20=
SIZE (gcc-esp-2021r2.tar.gz) = 102863056
SIZE (libelf-0.8.13.tar.gz) = 148529

155
devel/xtensa-esp32s3-elf/gcc/patches/patch-include_xtensa-config_h Normal file
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@ -0,0 +1,155 @@
xtensa-config.h for ESP32
Index: include/xtensa-config.h
--- include/xtensa-config.h.orig
+++ include/xtensa-config.h
@@ -1,5 +1,6 @@
/* Xtensa configuration settings.
- Copyright (C) 2001-2018 Free Software Foundation, Inc.
+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+ Free Software Foundation, Inc.
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
This program is free software; you can redistribute it and/or modify
@@ -25,7 +26,7 @@
macros. */
#undef XCHAL_HAVE_BE
-#define XCHAL_HAVE_BE 1
+#define XCHAL_HAVE_BE 0
#undef XCHAL_HAVE_DENSITY
#define XCHAL_HAVE_DENSITY 1
@@ -49,7 +50,7 @@
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#undef XCHAL_HAVE_MAC16
-#define XCHAL_HAVE_MAC16 0
+#define XCHAL_HAVE_MAC16 1
#undef XCHAL_HAVE_MUL16
#define XCHAL_HAVE_MUL16 1
@@ -58,7 +59,7 @@
#define XCHAL_HAVE_MUL32 1
#undef XCHAL_HAVE_MUL32_HIGH
-#define XCHAL_HAVE_MUL32_HIGH 0
+#define XCHAL_HAVE_MUL32_HIGH 1
#undef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 1
@@ -85,30 +86,37 @@
#define XCHAL_HAVE_S32C1I 1
#undef XCHAL_HAVE_BOOLEANS
-#define XCHAL_HAVE_BOOLEANS 0
+#define XCHAL_HAVE_BOOLEANS 1
#undef XCHAL_HAVE_FP
-#define XCHAL_HAVE_FP 0
+#define XCHAL_HAVE_FP 1
#undef XCHAL_HAVE_FP_DIV
-#define XCHAL_HAVE_FP_DIV 0
+#define XCHAL_HAVE_FP_DIV 1
#undef XCHAL_HAVE_FP_RECIP
-#define XCHAL_HAVE_FP_RECIP 0
+#define XCHAL_HAVE_FP_RECIP 1
#undef XCHAL_HAVE_FP_SQRT
-#define XCHAL_HAVE_FP_SQRT 0
+#define XCHAL_HAVE_FP_SQRT 1
#undef XCHAL_HAVE_FP_RSQRT
-#define XCHAL_HAVE_FP_RSQRT 0
+#define XCHAL_HAVE_FP_RSQRT 1
+#undef XCHAL_HAVE_FP_POSTINC
+#define XCHAL_HAVE_FP_POSTINC 1
+
+#undef XCHAL_HAVE_DFP_ACCEL
+#define XCHAL_HAVE_DFP_ACCEL 0
+/* For backward compatibility */
#undef XCHAL_HAVE_DFP_accel
-#define XCHAL_HAVE_DFP_accel 0
+#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
+
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
#undef XCHAL_NUM_AREGS
-#define XCHAL_NUM_AREGS 32
+#define XCHAL_NUM_AREGS 64
#undef XCHAL_HAVE_WIDE_BRANCHES
#define XCHAL_HAVE_WIDE_BRANCHES 0
@@ -118,34 +126,31 @@
#undef XCHAL_ICACHE_SIZE
-#define XCHAL_ICACHE_SIZE 16384
+#define XCHAL_ICACHE_SIZE 0
#undef XCHAL_DCACHE_SIZE
-#define XCHAL_DCACHE_SIZE 16384
+#define XCHAL_DCACHE_SIZE 0
#undef XCHAL_ICACHE_LINESIZE
-#define XCHAL_ICACHE_LINESIZE 32
+#define XCHAL_ICACHE_LINESIZE 16
#undef XCHAL_DCACHE_LINESIZE
-#define XCHAL_DCACHE_LINESIZE 32
+#define XCHAL_DCACHE_LINESIZE 16
#undef XCHAL_ICACHE_LINEWIDTH
-#define XCHAL_ICACHE_LINEWIDTH 5
+#define XCHAL_ICACHE_LINEWIDTH 4
#undef XCHAL_DCACHE_LINEWIDTH
-#define XCHAL_DCACHE_LINEWIDTH 5
+#define XCHAL_DCACHE_LINEWIDTH 4
#undef XCHAL_DCACHE_IS_WRITEBACK
-#define XCHAL_DCACHE_IS_WRITEBACK 1
+#define XCHAL_DCACHE_IS_WRITEBACK 0
#undef XCHAL_HAVE_MMU
-#define XCHAL_HAVE_MMU 1
+#define XCHAL_HAVE_MMU 0
-#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
-
#undef XCHAL_HAVE_DEBUG
#define XCHAL_HAVE_DEBUG 1
@@ -160,7 +165,7 @@
#undef XCHAL_MAX_INSTRUCTION_SIZE
-#define XCHAL_MAX_INSTRUCTION_SIZE 3
+#define XCHAL_MAX_INSTRUCTION_SIZE 4
#undef XCHAL_INST_FETCH_WIDTH
#define XCHAL_INST_FETCH_WIDTH 4
@@ -172,5 +177,16 @@
#define XSHAL_ABI XTHAL_ABI_WINDOWED
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
+
+
+#undef XCHAL_M_STAGE
+#define XCHAL_M_STAGE 2
+
+#undef XTENSA_MARCH_LATEST
+#define XTENSA_MARCH_LATEST 270012
+
+#undef XTENSA_MARCH_EARLIEST
+#define XTENSA_MARCH_EARLIEST 270012
+
#endif /* !XTENSA_CONFIG_H */

1
devel/xtensa-esp32s3-elf/gcc/pkg/DESCR Normal file
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@ -0,0 +1 @@
GNU cross compiler suite, configured for the xtensa-esp32s3-elf target.

1453
devel/xtensa-esp32s3-elf/gcc/pkg/PLIST Normal file
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File diff suppressed because it is too large Load Diff

30
devel/xtensa-esp32s3-elf/gdb/Makefile Normal file
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@ -0,0 +1,30 @@
COMMENT = gdb for ${CONFIG} cross-development
VERSION = 2.35.1.2021.2
PKGNAME = ${CONFIG}-gdb-${VERSION}
GH_ACCOUNT = espressif
GH_PROJECT = binutils-gdb
GH_TAGNAME = esp-2021r2-gdb
WANTLIB += ${COMPILER_LIBCXX} c curses expat m z
BUILD_DEPENDS = devel/libtool \
devel/bison \
devel/xtensa-esp32-elf/binutils
RUN_DEPENDS += devel/xtensa-esp32-elf/binutils
CONFIGURE_ARGS += --enable-commonbfdlib=no \
--with-cross-host=yes \
--disable-werror \
--without-guile \
--without-lzma \
--disable-binutils \
--disable-ld \
--disable-gas \
--disable-gprof \
--disable-install-libiberty \
--enable-gdb \
--enable-sim
.include <bsd.port.mk>

2
devel/xtensa-esp32s3-elf/gdb/distinfo Normal file
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@ -0,0 +1,2 @@
SHA256 (binutils-gdb-esp-2021r2-gdb.tar.gz) = FijYCbd4pYgHkw3rnGwxifr32CheWu9t9jvkFHyhhvg=
SIZE (binutils-gdb-esp-2021r2-gdb.tar.gz) = 59701067

49596
devel/xtensa-esp32s3-elf/gdb/patches/patch-bfd_xtensa-modules_c Normal file
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14
devel/xtensa-esp32s3-elf/gdb/patches/patch-gdb_Makefile_in Normal file
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@ -0,0 +1,14 @@
Link mpfr dynamically
Index: gdb/Makefile.in
--- gdb/Makefile.in.orig
+++ gdb/Makefile.in
@@ -199,7 +199,7 @@ LIBXXHASH = @LIBXXHASH@
LIBIPT = @LIBIPT@
# Where is libmpfr? This will be empty if libmpfr was not available.
-LIBMPFR = @LIBMPFR@
+LIBMPFR = @LTLIBMPFR@
# GNU source highlight library.
SRCHIGH_LIBS = @SRCHIGH_LIBS@

100
devel/xtensa-esp32s3-elf/gdb/patches/patch-gdb_gdbserver_xtensa-regmap_c Normal file
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@ -0,0 +1,100 @@
New file from espressif overlays.
Index: gdb/gdbserver/xtensa-regmap.c
--- gdb/gdbserver/xtensa-regmap.c.orig
+++ gdb/gdbserver/xtensa-regmap.c
@@ -0,0 +1,94 @@
+/* Customized table mapping between kernel xtregset and GDB register cache.
+
+ Customer ID=15128; Build=0x90f1f; Copyright (c) 2007-2010 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+
+typedef struct {
+ int gdb_regnum;
+ int gdb_offset;
+ int ptrace_cp_offset;
+ int ptrace_offset;
+ int size;
+ int coproc;
+ int dbnum;
+ char* name
+;} xtensa_regtable_t;
+
+#define XTENSA_ELF_XTREG_SIZE 320
+
+const xtensa_regtable_t xtensa_regmap_table[] = {
+ /* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
+ { 75, 300, 8, 8, 4, -1, 0x0204, "br" },
+ { 76, 304, 12, 12, 4, -1, 0x020c, "scompare1" },
+ { 77, 308, 0, 0, 4, -1, 0x0210, "acclo" },
+ { 78, 312, 4, 4, 4, -1, 0x0211, "acchi" },
+ { 79, 316, 16, 16, 4, -1, 0x0220, "m0" },
+ { 80, 320, 20, 20, 4, -1, 0x0221, "m1" },
+ { 81, 324, 24, 24, 4, -1, 0x0222, "m2" },
+ { 82, 328, 28, 28, 4, -1, 0x0223, "m3" },
+ { 84, 336, 8, 40, 4, 0, 0x0030, "f0" },
+ { 85, 340, 12, 44, 4, 0, 0x0031, "f1" },
+ { 86, 344, 16, 48, 4, 0, 0x0032, "f2" },
+ { 87, 348, 20, 52, 4, 0, 0x0033, "f3" },
+ { 88, 352, 24, 56, 4, 0, 0x0034, "f4" },
+ { 89, 356, 28, 60, 4, 0, 0x0035, "f5" },
+ { 90, 360, 32, 64, 4, 0, 0x0036, "f6" },
+ { 91, 364, 36, 68, 4, 0, 0x0037, "f7" },
+ { 92, 368, 40, 72, 4, 0, 0x0038, "f8" },
+ { 93, 372, 44, 76, 4, 0, 0x0039, "f9" },
+ { 94, 376, 48, 80, 4, 0, 0x003a, "f10" },
+ { 95, 380, 52, 84, 4, 0, 0x003b, "f11" },
+ { 96, 384, 56, 88, 4, 0, 0x003c, "f12" },
+ { 97, 388, 60, 92, 4, 0, 0x003d, "f13" },
+ { 98, 392, 64, 96, 4, 0, 0x003e, "f14" },
+ { 99, 396, 68, 100, 4, 0, 0x003f, "f15" },
+ { 100, 400, 0, 32, 4, 0, 0x03e8, "fcr" },
+ { 101, 404, 4, 36, 4, 0, 0x03e9, "fsr" },
+ { 102, 408, 0, 112, 4, 3, 0x0300, "accx_0" },
+ { 103, 412, 4, 116, 4, 3, 0x0301, "accx_1" },
+ { 104, 416, 8, 120, 4, 3, 0x0302, "qacc_h_0" },
+ { 105, 420, 12, 124, 4, 3, 0x0303, "qacc_h_1" },
+ { 106, 424, 16, 128, 4, 3, 0x0304, "qacc_h_2" },
+ { 107, 428, 20, 132, 4, 3, 0x0305, "qacc_h_3" },
+ { 108, 432, 24, 136, 4, 3, 0x0306, "qacc_h_4" },
+ { 109, 436, 28, 140, 4, 3, 0x0307, "qacc_l_0" },
+ { 110, 440, 32, 144, 4, 3, 0x0308, "qacc_l_1" },
+ { 111, 444, 36, 148, 4, 3, 0x0309, "qacc_l_2" },
+ { 112, 448, 40, 152, 4, 3, 0x030a, "qacc_l_3" },
+ { 113, 452, 44, 156, 4, 3, 0x030b, "qacc_l_4" },
+ { 114, 456, 48, 160, 4, 3, 0x030d, "sar_byte" },
+ { 115, 460, 52, 164, 4, 3, 0x030e, "fft_bit_width" },
+ { 116, 464, 56, 168, 4, 3, 0x030f, "ua_state_0" },
+ { 117, 468, 60, 172, 4, 3, 0x0310, "ua_state_1" },
+ { 118, 472, 64, 176, 4, 3, 0x0311, "ua_state_2" },
+ { 119, 476, 68, 180, 4, 3, 0x0312, "ua_state_3" },
+ { 120, 480, 80, 192, 16, 3, 0x1008, "q0" },
+ { 121, 496, 96, 208, 16, 3, 0x1009, "q1" },
+ { 122, 512, 112, 224, 16, 3, 0x100a, "q2" },
+ { 123, 528, 128, 240, 16, 3, 0x100b, "q3" },
+ { 124, 544, 144, 256, 16, 3, 0x100c, "q4" },
+ { 125, 560, 160, 272, 16, 3, 0x100d, "q5" },
+ { 126, 576, 176, 288, 16, 3, 0x100e, "q6" },
+ { 127, 592, 192, 304, 16, 3, 0x100f, "q7" },
+ { 0 }
+};
+

107
devel/xtensa-esp32s3-elf/gdb/patches/patch-gdb_gdbserver_xtensa-xtregs_c Normal file
View File

@ -0,0 +1,107 @@
Index: gdb/gdbserver/xtensa-xtregs.c
--- gdb/gdbserver/xtensa-xtregs.c.orig
+++ gdb/gdbserver/xtensa-xtregs.c
@@ -1,20 +1,25 @@
-/* Table mapping between kernel xtregset and GDB register cache.
- Copyright (C) 2007-2020 Free Software Foundation, Inc.
+/* Customized table mapping between kernel xtregset and GDB register cache.
- This file is part of GDB.
+ Customer ID=15128; Build=0x90f1f; Copyright (c) 2007-2010 Tensilica Inc.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 3 of the
- License, or (at your option) any later version.
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
typedef struct {
@@ -28,10 +33,62 @@ typedef struct {
char* name
;} xtensa_regtable_t;
-#define XTENSA_ELF_XTREG_SIZE 4
+#define XTENSA_ELF_XTREG_SIZE 320
const xtensa_regtable_t xtensa_regmap_table[] = {
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
- { 44, 176, 0, 0, 4, -1, 0x020c, "scompare1" },
+ { 75, 300, 8, 8, 4, -1, 0x0204, "br" },
+ { 76, 304, 12, 12, 4, -1, 0x020c, "scompare1" },
+ { 77, 308, 0, 0, 4, -1, 0x0210, "acclo" },
+ { 78, 312, 4, 4, 4, -1, 0x0211, "acchi" },
+ { 79, 316, 16, 16, 4, -1, 0x0220, "m0" },
+ { 80, 320, 20, 20, 4, -1, 0x0221, "m1" },
+ { 81, 324, 24, 24, 4, -1, 0x0222, "m2" },
+ { 82, 328, 28, 28, 4, -1, 0x0223, "m3" },
+ { 84, 336, 8, 40, 4, 0, 0x0030, "f0" },
+ { 85, 340, 12, 44, 4, 0, 0x0031, "f1" },
+ { 86, 344, 16, 48, 4, 0, 0x0032, "f2" },
+ { 87, 348, 20, 52, 4, 0, 0x0033, "f3" },
+ { 88, 352, 24, 56, 4, 0, 0x0034, "f4" },
+ { 89, 356, 28, 60, 4, 0, 0x0035, "f5" },
+ { 90, 360, 32, 64, 4, 0, 0x0036, "f6" },
+ { 91, 364, 36, 68, 4, 0, 0x0037, "f7" },
+ { 92, 368, 40, 72, 4, 0, 0x0038, "f8" },
+ { 93, 372, 44, 76, 4, 0, 0x0039, "f9" },
+ { 94, 376, 48, 80, 4, 0, 0x003a, "f10" },
+ { 95, 380, 52, 84, 4, 0, 0x003b, "f11" },
+ { 96, 384, 56, 88, 4, 0, 0x003c, "f12" },
+ { 97, 388, 60, 92, 4, 0, 0x003d, "f13" },
+ { 98, 392, 64, 96, 4, 0, 0x003e, "f14" },
+ { 99, 396, 68, 100, 4, 0, 0x003f, "f15" },
+ { 100, 400, 0, 32, 4, 0, 0x03e8, "fcr" },
+ { 101, 404, 4, 36, 4, 0, 0x03e9, "fsr" },
+ { 102, 408, 0, 112, 4, 3, 0x0300, "accx_0" },
+ { 103, 412, 4, 116, 4, 3, 0x0301, "accx_1" },
+ { 104, 416, 8, 120, 4, 3, 0x0302, "qacc_h_0" },
+ { 105, 420, 12, 124, 4, 3, 0x0303, "qacc_h_1" },
+ { 106, 424, 16, 128, 4, 3, 0x0304, "qacc_h_2" },
+ { 107, 428, 20, 132, 4, 3, 0x0305, "qacc_h_3" },
+ { 108, 432, 24, 136, 4, 3, 0x0306, "qacc_h_4" },
+ { 109, 436, 28, 140, 4, 3, 0x0307, "qacc_l_0" },
+ { 110, 440, 32, 144, 4, 3, 0x0308, "qacc_l_1" },
+ { 111, 444, 36, 148, 4, 3, 0x0309, "qacc_l_2" },
+ { 112, 448, 40, 152, 4, 3, 0x030a, "qacc_l_3" },
+ { 113, 452, 44, 156, 4, 3, 0x030b, "qacc_l_4" },
+ { 114, 456, 48, 160, 4, 3, 0x030d, "sar_byte" },
+ { 115, 460, 52, 164, 4, 3, 0x030e, "fft_bit_width" },
+ { 116, 464, 56, 168, 4, 3, 0x030f, "ua_state_0" },
+ { 117, 468, 60, 172, 4, 3, 0x0310, "ua_state_1" },
+ { 118, 472, 64, 176, 4, 3, 0x0311, "ua_state_2" },
+ { 119, 476, 68, 180, 4, 3, 0x0312, "ua_state_3" },
+ { 120, 480, 80, 192, 16, 3, 0x1008, "q0" },
+ { 121, 496, 96, 208, 16, 3, 0x1009, "q1" },
+ { 122, 512, 112, 224, 16, 3, 0x100a, "q2" },
+ { 123, 528, 128, 240, 16, 3, 0x100b, "q3" },
+ { 124, 544, 144, 256, 16, 3, 0x100c, "q4" },
+ { 125, 560, 160, 272, 16, 3, 0x100d, "q5" },
+ { 126, 576, 176, 288, 16, 3, 0x100e, "q6" },
+ { 127, 592, 192, 304, 16, 3, 0x100f, "q7" },
{ 0 }
};
+

105
devel/xtensa-esp32s3-elf/gdb/patches/patch-gdb_regformats_reg-xtensa_dat Normal file
View File

@ -0,0 +1,105 @@
Index: gdb/regformats/reg-xtensa.dat
--- gdb/regformats/reg-xtensa.dat.orig
+++ gdb/regformats/reg-xtensa.dat
@@ -33,15 +33,98 @@ expedite:pc,windowbase,windowstart
32:ar29
32:ar30
32:ar31
+32:ar32
+32:ar33
+32:ar34
+32:ar35
+32:ar36
+32:ar37
+32:ar38
+32:ar39
+32:ar40
+32:ar41
+32:ar42
+32:ar43
+32:ar44
+32:ar45
+32:ar46
+32:ar47
+32:ar48
+32:ar49
+32:ar50
+32:ar51
+32:ar52
+32:ar53
+32:ar54
+32:ar55
+32:ar56
+32:ar57
+32:ar58
+32:ar59
+32:ar60
+32:ar61
+32:ar62
+32:ar63
32:lbeg
32:lend
32:lcount
32:sar
-32:litbase
32:windowbase
32:windowstart
-32:sr176
-32:sr208
+32:configid0
+32:configid1
32:ps
32:threadptr
+32:br
32:scompare1
+32:acclo
+32:acchi
+32:m0
+32:m1
+32:m2
+32:m3
+32:gpio_out
+32:f0
+32:f1
+32:f2
+32:f3
+32:f4
+32:f5
+32:f6
+32:f7
+32:f8
+32:f9
+32:f10
+32:f11
+32:f12
+32:f13
+32:f14
+32:f15
+32:fcr
+32:fsr
+32:accx_0
+32:accx_1
+32:qacc_h_0
+32:qacc_h_1
+32:qacc_h_2
+32:qacc_h_3
+32:qacc_h_4
+32:qacc_l_0
+32:qacc_l_1
+32:qacc_l_2
+32:qacc_l_3
+32:qacc_l_4
+32:sar_byte
+32:fft_bit_width
+32:ua_state_0
+32:ua_state_1
+32:ua_state_2
+32:ua_state_3
+128:q0
+128:q1
+128:q2
+128:q3
+128:q4
+128:q5
+128:q6
+128:q7

609
devel/xtensa-esp32s3-elf/gdb/patches/patch-gdb_xtensa-config_c Normal file
View File

@ -0,0 +1,609 @@
Index: gdb/xtensa-config.c
--- gdb/xtensa-config.c.orig
+++ gdb/xtensa-config.c
@@ -1,71 +1,128 @@
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
- Copyright (C) 2003-2020 Free Software Foundation, Inc.
+ Customer ID=15128; Build=0x90f1f; Copyright (c) 2003-2021 Tensilica Inc.
- This file is part of GDB.
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
-#include "defs.h"
-
#define XTENSA_CONFIG_VERSION 0x60
+#include "defs.h"
#include "xtensa-config.h"
#include "xtensa-tdep.h"
/* Masked registers. */
-xtensa_reg_mask_t xtensa_submask0[] = { { 42, 0, 4 } };
+xtensa_reg_mask_t xtensa_submask0[] = { { 75, 0, 1 } };
const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
-xtensa_reg_mask_t xtensa_submask1[] = { { 42, 5, 1 } };
+xtensa_reg_mask_t xtensa_submask1[] = { { 75, 1, 1 } };
const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
-xtensa_reg_mask_t xtensa_submask2[] = { { 42, 18, 1 } };
+xtensa_reg_mask_t xtensa_submask2[] = { { 75, 2, 1 } };
const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
-xtensa_reg_mask_t xtensa_submask3[] = { { 42, 6, 2 } };
+xtensa_reg_mask_t xtensa_submask3[] = { { 75, 3, 1 } };
const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
-xtensa_reg_mask_t xtensa_submask4[] = { { 42, 4, 1 } };
+xtensa_reg_mask_t xtensa_submask4[] = { { 75, 4, 1 } };
const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
-xtensa_reg_mask_t xtensa_submask5[] = { { 42, 16, 2 } };
+xtensa_reg_mask_t xtensa_submask5[] = { { 75, 5, 1 } };
const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
-xtensa_reg_mask_t xtensa_submask6[] = { { 42, 8, 4 } };
+xtensa_reg_mask_t xtensa_submask6[] = { { 75, 6, 1 } };
const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
-xtensa_reg_mask_t xtensa_submask7[] = { { 37, 12, 20 } };
+xtensa_reg_mask_t xtensa_submask7[] = { { 75, 7, 1 } };
const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
-xtensa_reg_mask_t xtensa_submask8[] = { { 37, 0, 1 } };
+xtensa_reg_mask_t xtensa_submask8[] = { { 75, 8, 1 } };
const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
-xtensa_reg_mask_t xtensa_submask9[] = { { 86, 8, 4 } };
+xtensa_reg_mask_t xtensa_submask9[] = { { 75, 9, 1 } };
const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
-xtensa_reg_mask_t xtensa_submask10[] = { { 47, 24, 8 } };
+xtensa_reg_mask_t xtensa_submask10[] = { { 75, 10, 1 } };
const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
-xtensa_reg_mask_t xtensa_submask11[] = { { 47, 16, 8 } };
+xtensa_reg_mask_t xtensa_submask11[] = { { 75, 11, 1 } };
const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
-xtensa_reg_mask_t xtensa_submask12[] = { { 47, 8, 8 } };
+xtensa_reg_mask_t xtensa_submask12[] = { { 75, 12, 1 } };
const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
-xtensa_reg_mask_t xtensa_submask13[] = { { 48, 16, 2 } };
+xtensa_reg_mask_t xtensa_submask13[] = { { 75, 13, 1 } };
const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
-xtensa_reg_mask_t xtensa_submask14[] = { { 49, 16, 2 } };
+xtensa_reg_mask_t xtensa_submask14[] = { { 75, 14, 1 } };
const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
-xtensa_reg_mask_t xtensa_submask15[] = { { 45, 22, 10 } };
+xtensa_reg_mask_t xtensa_submask15[] = { { 75, 15, 1 } };
const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
+xtensa_reg_mask_t xtensa_submask16[] = { { 73, 0, 4 } };
+const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };
+xtensa_reg_mask_t xtensa_submask17[] = { { 73, 5, 1 } };
+const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };
+xtensa_reg_mask_t xtensa_submask18[] = { { 73, 18, 1 } };
+const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };
+xtensa_reg_mask_t xtensa_submask19[] = { { 73, 4, 1 } };
+const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };
+xtensa_reg_mask_t xtensa_submask20[] = { { 73, 16, 2 } };
+const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };
+xtensa_reg_mask_t xtensa_submask21[] = { { 73, 8, 4 } };
+const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };
+xtensa_reg_mask_t xtensa_submask22[] = { { 77, 0, 32 }, { 78, 0, 8 } };
+const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 };
+xtensa_reg_mask_t xtensa_submask23[] = { { 167, 8, 4 } };
+const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };
+xtensa_reg_mask_t xtensa_submask24[] = { { 100, 0, 2 } };
+const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 };
+xtensa_reg_mask_t xtensa_submask25[] = { { 100, 6, 1 } };
+const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 };
+xtensa_reg_mask_t xtensa_submask26[] = { { 100, 5, 1 } };
+const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };
+xtensa_reg_mask_t xtensa_submask27[] = { { 100, 4, 1 } };
+const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };
+xtensa_reg_mask_t xtensa_submask28[] = { { 100, 3, 1 } };
+const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };
+xtensa_reg_mask_t xtensa_submask29[] = { { 100, 2, 1 } };
+const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };
+xtensa_reg_mask_t xtensa_submask30[] = { { 101, 11, 1 } };
+const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };
+xtensa_reg_mask_t xtensa_submask31[] = { { 101, 10, 1 } };
+const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 };
+xtensa_reg_mask_t xtensa_submask32[] = { { 101, 9, 1 } };
+const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 };
+xtensa_reg_mask_t xtensa_submask33[] = { { 101, 8, 1 } };
+const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 };
+xtensa_reg_mask_t xtensa_submask34[] = { { 101, 7, 1 } };
+const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 };
+xtensa_reg_mask_t xtensa_submask35[] = { { 100, 12, 20 } };
+const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 };
+xtensa_reg_mask_t xtensa_submask36[] = { { 101, 12, 20 } };
+const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 };
+xtensa_reg_mask_t xtensa_submask37[] = { { 100, 7, 5 } };
+const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 };
+xtensa_reg_mask_t xtensa_submask38[] = { { 101, 0, 7 } };
+const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 };
+xtensa_reg_mask_t xtensa_submask39[] = { { 102, 0, 32 }, { 103, 0, 8 } };
+const xtensa_mask_t xtensa_mask39 = { 2, xtensa_submask39 };
+xtensa_reg_mask_t xtensa_submask40[] = { { 104, 0, 32 }, { 105, 0, 32 }, { 106, 0, 32 }, { 107, 0, 32 }, { 108, 0, 32 } };
+const xtensa_mask_t xtensa_mask40 = { 5, xtensa_submask40 };
+xtensa_reg_mask_t xtensa_submask41[] = { { 109, 0, 32 }, { 110, 0, 32 }, { 111, 0, 32 }, { 112, 0, 32 }, { 113, 0, 32 } };
+const xtensa_mask_t xtensa_mask41 = { 5, xtensa_submask41 };
+xtensa_reg_mask_t xtensa_submask42[] = { { 116, 0, 32 }, { 117, 0, 32 }, { 118, 0, 32 }, { 119, 0, 32 } };
+const xtensa_mask_t xtensa_mask42 = { 4, xtensa_submask42 };
/* Register map. */
xtensa_register_t rmap[] =
{
/* idx ofs bi sz al targno flags cp typ group name */
- XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
+ XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0)
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
@@ -98,124 +155,347 @@ xtensa_register_t rmap[] =
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
- XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
- XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
- XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
- XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
- XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
- XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
- XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
- XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0)
- XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0)
- XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
- XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
- XTREG( 44,176,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
- XTREG( 45,180,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
- XTREG( 46,184,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
- XTREG( 47,188,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
- XTREG( 48,192,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
- XTREG( 49,196,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
- XTREG( 50,200, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
- XTREG( 51,204,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
- XTREG( 52,208,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
- XTREG( 53,212,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
- XTREG( 54,216,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
- XTREG( 55,220,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
- XTREG( 56,224,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
- XTREG( 57,228,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
- XTREG( 58,232,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
- XTREG( 59,236,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
- XTREG( 60,240,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
- XTREG( 61,244,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
- XTREG( 62,248,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
- XTREG( 63,252,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
- XTREG( 64,256,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
- XTREG( 65,260,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
- XTREG( 66,264,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
- XTREG( 67,268,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
- XTREG( 68,272,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
- XTREG( 69,276,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
- XTREG( 70,280,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
- XTREG( 71,284,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
- XTREG( 72,288,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
- XTREG( 73,292,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
- XTREG( 74,296,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
- XTREG( 75,300,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
- XTREG( 76,304,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
- XTREG( 77,308,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
- XTREG( 78,312,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
- XTREG( 79,316, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
- XTREG( 80,320,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
- XTREG( 81,324,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
- XTREG( 82,328,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
- XTREG( 83,332,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
- XTREG( 84,336,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
- XTREG( 85,340, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
- XTREG( 86,344,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
- XTREG( 87,348,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
- XTREG( 88,352,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
- XTREG( 89,356,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
- XTREG( 90,360, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
- XTREG( 91,364,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
- XTREG( 92,368,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
- XTREG( 93,372,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
- XTREG( 94,376,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
- XTREG( 95,380,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
- XTREG( 96,384,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
- XTREG( 97,388,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
- XTREG( 98,392,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
- XTREG( 99,396,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
- XTREG(100,400,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
- XTREG(101,404,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
- XTREG(102,408,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
- XTREG(103,412,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
- XTREG(104,416,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
- XTREG(105,420,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
- XTREG(106,424,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
- XTREG(107,428,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
- XTREG(108,432,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
- XTREG(109,436,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
- XTREG(110,440,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
- XTREG(111,444,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
- XTREG(112,448,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
- XTREG(113,452, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
+ XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32, 0,0,0,0,0,0)
+ XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33, 0,0,0,0,0,0)
+ XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34, 0,0,0,0,0,0)
+ XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35, 0,0,0,0,0,0)
+ XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36, 0,0,0,0,0,0)
+ XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37, 0,0,0,0,0,0)
+ XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38, 0,0,0,0,0,0)
+ XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39, 0,0,0,0,0,0)
+ XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40, 0,0,0,0,0,0)
+ XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41, 0,0,0,0,0,0)
+ XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42, 0,0,0,0,0,0)
+ XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43, 0,0,0,0,0,0)
+ XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44, 0,0,0,0,0,0)
+ XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45, 0,0,0,0,0,0)
+ XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46, 0,0,0,0,0,0)
+ XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47, 0,0,0,0,0,0)
+ XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48, 0,0,0,0,0,0)
+ XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49, 0,0,0,0,0,0)
+ XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50, 0,0,0,0,0,0)
+ XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51, 0,0,0,0,0,0)
+ XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52, 0,0,0,0,0,0)
+ XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53, 0,0,0,0,0,0)
+ XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54, 0,0,0,0,0,0)
+ XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55, 0,0,0,0,0,0)
+ XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56, 0,0,0,0,0,0)
+ XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57, 0,0,0,0,0,0)
+ XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58, 0,0,0,0,0,0)
+ XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59, 0,0,0,0,0,0)
+ XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60, 0,0,0,0,0,0)
+ XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61, 0,0,0,0,0,0)
+ XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62, 0,0,0,0,0,0)
+ XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63, 0,0,0,0,0,0)
+ XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
+ XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
+ XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
+ XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
+ XTREG( 69,276, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
+ XTREG( 70,280,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
+ XTREG( 71,284,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
+ XTREG( 72,288,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
+ XTREG( 73,292,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
+ XTREG( 74,296,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
+ XTREG( 75,300,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
+ XTREG( 76,304,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
+ XTREG( 77,308,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
+ XTREG( 78,312, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
+ XTREG( 79,316,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
+ XTREG( 80,320,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
+ XTREG( 81,324,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
+ XTREG( 82,328,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
+ XTREG( 83,332, 8, 4, 4,0x030c,0x000e,-1, 3,0x0210,gpio_out, 0,0,0,0,0,0)
+ XTREG( 84,336,32, 4, 4,0x0030,0x0006, 0, 4,0x0401,f0,
+ "03:03:44:00","03:03:04:00",0,0,0,0)
+ XTREG( 85,340,32, 4, 4,0x0031,0x0006, 0, 4,0x0401,f1,
+ "03:13:44:00","03:13:04:00",0,0,0,0)
+ XTREG( 86,344,32, 4, 4,0x0032,0x0006, 0, 4,0x0401,f2,
+ "03:23:44:00","03:23:04:00",0,0,0,0)
+ XTREG( 87,348,32, 4, 4,0x0033,0x0006, 0, 4,0x0401,f3,
+ "03:33:44:00","03:33:04:00",0,0,0,0)
+ XTREG( 88,352,32, 4, 4,0x0034,0x0006, 0, 4,0x0401,f4,
+ "03:43:44:00","03:43:04:00",0,0,0,0)
+ XTREG( 89,356,32, 4, 4,0x0035,0x0006, 0, 4,0x0401,f5,
+ "03:53:44:00","03:53:04:00",0,0,0,0)
+ XTREG( 90,360,32, 4, 4,0x0036,0x0006, 0, 4,0x0401,f6,
+ "03:63:44:00","03:63:04:00",0,0,0,0)
+ XTREG( 91,364,32, 4, 4,0x0037,0x0006, 0, 4,0x0401,f7,
+ "03:73:44:00","03:73:04:00",0,0,0,0)
+ XTREG( 92,368,32, 4, 4,0x0038,0x0006, 0, 4,0x0401,f8,
+ "03:83:44:00","03:83:04:00",0,0,0,0)
+ XTREG( 93,372,32, 4, 4,0x0039,0x0006, 0, 4,0x0401,f9,
+ "03:93:44:00","03:93:04:00",0,0,0,0)
+ XTREG( 94,376,32, 4, 4,0x003a,0x0006, 0, 4,0x0401,f10,
+ "03:a3:44:00","03:a3:04:00",0,0,0,0)
+ XTREG( 95,380,32, 4, 4,0x003b,0x0006, 0, 4,0x0401,f11,
+ "03:b3:44:00","03:b3:04:00",0,0,0,0)
+ XTREG( 96,384,32, 4, 4,0x003c,0x0006, 0, 4,0x0401,f12,
+ "03:c3:44:00","03:c3:04:00",0,0,0,0)
+ XTREG( 97,388,32, 4, 4,0x003d,0x0006, 0, 4,0x0401,f13,
+ "03:d3:44:00","03:d3:04:00",0,0,0,0)
+ XTREG( 98,392,32, 4, 4,0x003e,0x0006, 0, 4,0x0401,f14,
+ "03:e3:44:00","03:e3:04:00",0,0,0,0)
+ XTREG( 99,396,32, 4, 4,0x003f,0x0006, 0, 4,0x0401,f15,
+ "03:f3:44:00","03:f3:04:00",0,0,0,0)
+ XTREG(100,400,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr, 0,0,0,0,0,0)
+ XTREG(101,404,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr, 0,0,0,0,0,0)
+ XTREG(102,408,32, 4, 4,0x0300,0x0006, 3, 3,0x0200,accx_0, 0,0,0,0,0,0)
+ XTREG(103,412, 8, 4, 4,0x0301,0x0006, 3, 3,0x0200,accx_1, 0,0,0,0,0,0)
+ XTREG(104,416,32, 4, 4,0x0302,0x0006, 3, 3,0x0200,qacc_h_0, 0,0,0,0,0,0)
+ XTREG(105,420,32, 4, 4,0x0303,0x0006, 3, 3,0x0200,qacc_h_1, 0,0,0,0,0,0)
+ XTREG(106,424,32, 4, 4,0x0304,0x0006, 3, 3,0x0200,qacc_h_2, 0,0,0,0,0,0)
+ XTREG(107,428,32, 4, 4,0x0305,0x0006, 3, 3,0x0200,qacc_h_3, 0,0,0,0,0,0)
+ XTREG(108,432,32, 4, 4,0x0306,0x0006, 3, 3,0x0200,qacc_h_4, 0,0,0,0,0,0)
+ XTREG(109,436,32, 4, 4,0x0307,0x0006, 3, 3,0x0200,qacc_l_0, 0,0,0,0,0,0)
+ XTREG(110,440,32, 4, 4,0x0308,0x0006, 3, 3,0x0200,qacc_l_1, 0,0,0,0,0,0)
+ XTREG(111,444,32, 4, 4,0x0309,0x0006, 3, 3,0x0200,qacc_l_2, 0,0,0,0,0,0)
+ XTREG(112,448,32, 4, 4,0x030a,0x0006, 3, 3,0x0200,qacc_l_3, 0,0,0,0,0,0)
+ XTREG(113,452,32, 4, 4,0x030b,0x0006, 3, 3,0x0200,qacc_l_4, 0,0,0,0,0,0)
+ XTREG(114,456, 4, 4, 4,0x030d,0x0006, 3, 3,0x0210,sar_byte, 0,0,0,0,0,0)
+ XTREG(115,460, 4, 4, 4,0x030e,0x0006, 3, 3,0x0210,fft_bit_width,0,0,0,0,0,0)
+ XTREG(116,464,32, 4, 4,0x030f,0x0006, 3, 3,0x0200,ua_state_0, 0,0,0,0,0,0)
+ XTREG(117,468,32, 4, 4,0x0310,0x0006, 3, 3,0x0200,ua_state_1, 0,0,0,0,0,0)
+ XTREG(118,472,32, 4, 4,0x0311,0x0006, 3, 3,0x0200,ua_state_2, 0,0,0,0,0,0)
+ XTREG(119,476,32, 4, 4,0x0312,0x0006, 3, 3,0x0200,ua_state_3, 0,0,0,0,0,0)
+ XTREG(120,480,128,16,16,0x1008,0x0006, 3, 4,0x0201,q0,
+ "03:44:60:cd","03:44:20:cd",0,0,0,0)
+ XTREG(121,496,128,16,16,0x1009,0x0006, 3, 4,0x0201,q1,
+ "03:44:e0:cd","03:44:a0:cd",0,0,0,0)
+ XTREG(122,512,128,16,16,0x100a,0x0006, 3, 4,0x0201,q2,
+ "03:44:60:dd","03:44:20:dd",0,0,0,0)
+ XTREG(123,528,128,16,16,0x100b,0x0006, 3, 4,0x0201,q3,
+ "03:44:e0:dd","03:44:a0:dd",0,0,0,0)
+ XTREG(124,544,128,16,16,0x100c,0x0006, 3, 4,0x0201,q4,
+ "03:44:60:ed","03:44:20:ed",0,0,0,0)
+ XTREG(125,560,128,16,16,0x100d,0x0006, 3, 4,0x0201,q5,
+ "03:44:e0:ed","03:44:a0:ed",0,0,0,0)
+ XTREG(126,576,128,16,16,0x100e,0x0006, 3, 4,0x0201,q6,
+ "03:44:60:fd","03:44:20:fd",0,0,0,0)
+ XTREG(127,592,128,16,16,0x100f,0x0006, 3, 4,0x0201,q7,
+ "03:44:e0:fd","03:44:a0:fd",0,0,0,0)
+ XTREG(128,608,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
+ XTREG(129,612, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
+ XTREG(130,616, 1, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl, 0,0,0,0,0,0)
+ XTREG(131,620, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
+ XTREG(132,624,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
+ XTREG(133,628,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
+ XTREG(134,632,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
+ XTREG(135,636,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
+ XTREG(136,640,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
+ XTREG(137,644,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
+ XTREG(138,648,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
+ XTREG(139,652,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
+ XTREG(140,656,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
+ XTREG(141,660,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
+ XTREG(142,664,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
+ XTREG(143,668,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
+ XTREG(144,672,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
+ XTREG(145,676,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
+ XTREG(146,680,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
+ XTREG(147,684,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
+ XTREG(148,688,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
+ XTREG(149,692,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
+ XTREG(150,696,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
+ XTREG(151,700,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
+ XTREG(152,704,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
+ XTREG(153,708,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
+ XTREG(154,712,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
+ XTREG(155,716,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
+ XTREG(156,720,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
+ XTREG(157,724,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
+ XTREG(158,728,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
+ XTREG(159,732,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
+ XTREG(160,736, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
+ XTREG(161,740,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
+ XTREG(162,744,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
+ XTREG(163,748,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
+ XTREG(164,752,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
+ XTREG(165,756,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
+ XTREG(166,760, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
+ XTREG(167,764,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
+ XTREG(168,768,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
+ XTREG(169,772,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
+ XTREG(170,776,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
+ XTREG(171,780, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
+ XTREG(172,784,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
+ XTREG(173,788,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
+ XTREG(174,792,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
+ XTREG(175,796,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
+ XTREG(176,800,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
+ XTREG(177,804,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
+ XTREG(178,808,32, 4, 4,0x02f6,0x0007,-2, 2,0x1000,misc2, 0,0,0,0,0,0)
+ XTREG(179,812,32, 4, 4,0x02f7,0x0007,-2, 2,0x1000,misc3, 0,0,0,0,0,0)
+ XTREG(180,816,32, 4, 4,0x2028,0x000f,-2, 4,0x0101,pwrctl,
+ "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(181,820,32, 4, 4,0x2029,0x000f,-2, 4,0x0101,pwrstat,
+ "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(182,824, 1, 4, 4,0x202a,0x000f,-2, 4,0x0101,eristat,
+ "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(183,828,32, 4, 4,0x202b,0x000f,-2, 4,0x0101,cs_itctrl,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(184,832,16, 4, 4,0x202c,0x000f,-2, 4,0x0101,cs_claimset,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(185,836,16, 4, 4,0x202d,0x000f,-2, 4,0x0101,cs_claimclr,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(186,840,32, 4, 4,0x202e,0x000d,-2, 4,0x0101,cs_lockaccess,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(187,844,32, 4, 4,0x202f,0x000b,-2, 4,0x0101,cs_lockstatus,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(188,848, 1, 4, 4,0x2030,0x000b,-2, 4,0x0101,cs_authstatus,
+ "03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(189,852,32, 4, 4,0x203f,0x000f,-2, 4,0x0101,fault_info,
+ "03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(190,856,32, 4, 4,0x2040,0x0003,-2, 4,0x0101,trax_id,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(191,860,32, 4, 4,0x2041,0x000f,-2, 4,0x0101,trax_control,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(192,864,32, 4, 4,0x2042,0x000b,-2, 4,0x0101,trax_status,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(193,868,32, 4, 4,0x2043,0x000f,-2, 4,0x0101,trax_data,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(194,872,32, 4, 4,0x2044,0x000f,-2, 4,0x0101,trax_address,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(195,876,32, 4, 4,0x2045,0x000f,-2, 4,0x0101,trax_pctrigger,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(196,880,32, 4, 4,0x2046,0x000f,-2, 4,0x0101,trax_pcmatch,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(197,884,32, 4, 4,0x2047,0x000f,-2, 4,0x0101,trax_delay,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(198,888,32, 4, 4,0x2048,0x000f,-2, 4,0x0101,trax_memstart,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(199,892,32, 4, 4,0x2049,0x000f,-2, 4,0x0101,trax_memend,
+ "03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(200,896,32, 4, 4,0x2057,0x000f,-2, 4,0x0101,pmg,
+ "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(201,900,32, 4, 4,0x2058,0x000f,-2, 4,0x0101,pmpc,
+ "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(202,904,32, 4, 4,0x2059,0x000f,-2, 4,0x0101,pm0,
+ "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(203,908,32, 4, 4,0x205a,0x000f,-2, 4,0x0101,pm1,
+ "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(204,912,32, 4, 4,0x205b,0x000f,-2, 4,0x0101,pmctrl0,
+ "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(205,916,32, 4, 4,0x205c,0x000f,-2, 4,0x0101,pmctrl1,
+ "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(206,920,32, 4, 4,0x205d,0x000f,-2, 4,0x0101,pmstat0,
+ "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(207,924,32, 4, 4,0x205e,0x000f,-2, 4,0x0101,pmstat1,
+ "03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(208,928,32, 4, 4,0x205f,0x0003,-2, 4,0x0101,ocdid,
+ "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(209,932,32, 4, 4,0x2060,0x000f,-2, 4,0x0101,ocd_dcrclr,
+ "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(210,936,32, 4, 4,0x2061,0x000f,-2, 4,0x0101,ocd_dcrset,
+ "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(211,940,32, 4, 4,0x2062,0x000f,-2, 4,0x0101,ocd_dsr,
+ "03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+ XTREG(212,944,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0, 0,0,0,0,0,0)
+ XTREG(213,948,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1, 0,0,0,0,0,0)
+ XTREG(214,952,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2, 0,0,0,0,0,0)
+ XTREG(215,956,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3, 0,0,0,0,0,0)
+ XTREG(216,960,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4, 0,0,0,0,0,0)
+ XTREG(217,964,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5, 0,0,0,0,0,0)
+ XTREG(218,968,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6, 0,0,0,0,0,0)
+ XTREG(219,972,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7, 0,0,0,0,0,0)
+ XTREG(220,976,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8, 0,0,0,0,0,0)
+ XTREG(221,980,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9, 0,0,0,0,0,0)
+ XTREG(222,984,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10, 0,0,0,0,0,0)
+ XTREG(223,988,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11, 0,0,0,0,0,0)
+ XTREG(224,992,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12, 0,0,0,0,0,0)
+ XTREG(225,996,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13, 0,0,0,0,0,0)
+ XTREG(226,1000,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14, 0,0,0,0,0,0)
+ XTREG(227,1004,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15, 0,0,0,0,0,0)
+ XTREG(228,1008, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
0,0,&xtensa_mask0,0,0,0)
- XTREG(114,456, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
+ XTREG(229,1009, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
0,0,&xtensa_mask1,0,0,0)
- XTREG(115,460, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
+ XTREG(230,1010, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
0,0,&xtensa_mask2,0,0,0)
- XTREG(116,464, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring,
+ XTREG(231,1011, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
0,0,&xtensa_mask3,0,0,0)
- XTREG(117,468, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm,
+ XTREG(232,1012, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
0,0,&xtensa_mask4,0,0,0)
- XTREG(118,472, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc,
+ XTREG(233,1013, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
0,0,&xtensa_mask5,0,0,0)
- XTREG(119,476, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb,
+ XTREG(234,1014, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
0,0,&xtensa_mask6,0,0,0)
- XTREG(120,480,20, 4, 4,0x200f,0x0006,-2, 6,0x1010,litbaddr,
+ XTREG(235,1015, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
0,0,&xtensa_mask7,0,0,0)
- XTREG(121,484, 1, 4, 4,0x2010,0x0006,-2, 6,0x1010,litben,
+ XTREG(236,1016, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
0,0,&xtensa_mask8,0,0,0)
- XTREG(122,488, 4, 4, 4,0x2015,0x0006,-2, 6,0x1010,dbnum,
+ XTREG(237,1017, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
0,0,&xtensa_mask9,0,0,0)
- XTREG(123,492, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid3,
+ XTREG(238,1018, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
0,0,&xtensa_mask10,0,0,0)
- XTREG(124,496, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid2,
+ XTREG(239,1019, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
0,0,&xtensa_mask11,0,0,0)
- XTREG(125,500, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid1,
+ XTREG(240,1020, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
0,0,&xtensa_mask12,0,0,0)
- XTREG(126,504, 2, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid4,
+ XTREG(241,1021, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
0,0,&xtensa_mask13,0,0,0)
- XTREG(127,508, 2, 4, 4,0x201a,0x0006,-2, 6,0x1010,datapgszid4,
+ XTREG(242,1022, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
0,0,&xtensa_mask14,0,0,0)
- XTREG(128,512,10, 4, 4,0x201b,0x0006,-2, 6,0x1010,ptbase,
+ XTREG(243,1023, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
0,0,&xtensa_mask15,0,0,0)
+ XTREG(244,1024, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
+ 0,0,&xtensa_mask16,0,0,0)
+ XTREG(245,1028, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
+ 0,0,&xtensa_mask17,0,0,0)
+ XTREG(246,1032, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
+ 0,0,&xtensa_mask18,0,0,0)
+ XTREG(247,1036, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
+ 0,0,&xtensa_mask19,0,0,0)
+ XTREG(248,1040, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
+ 0,0,&xtensa_mask20,0,0,0)
+ XTREG(249,1044, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
+ 0,0,&xtensa_mask21,0,0,0)
+ XTREG(250,1048,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,
+ 0,0,&xtensa_mask22,0,0,0)
+ XTREG(251,1056, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum,
+ 0,0,&xtensa_mask23,0,0,0)
+ XTREG(252,1060, 2, 4, 4,0x2015,0x0006, 0, 5,0x1010,roundmode,
+ 0,0,&xtensa_mask24,0,0,0)
+ XTREG(253,1064, 1, 4, 4,0x2016,0x0006, 0, 5,0x1010,invalidenable,
+ 0,0,&xtensa_mask25,0,0,0)
+ XTREG(254,1068, 1, 4, 4,0x2017,0x0006, 0, 5,0x1010,divzeroenable,
+ 0,0,&xtensa_mask26,0,0,0)
+ XTREG(255,1072, 1, 4, 4,0x2018,0x0006, 0, 5,0x1010,overflowenable,
+ 0,0,&xtensa_mask27,0,0,0)
+ XTREG(256,1076, 1, 4, 4,0x2019,0x0006, 0, 5,0x1010,underflowenable,
+ 0,0,&xtensa_mask28,0,0,0)
+ XTREG(257,1080, 1, 4, 4,0x201a,0x0006, 0, 5,0x1010,inexactenable,
+ 0,0,&xtensa_mask29,0,0,0)
+ XTREG(258,1084, 1, 4, 4,0x201b,0x0006, 0, 5,0x1010,invalidflag,
+ 0,0,&xtensa_mask30,0,0,0)
+ XTREG(259,1088, 1, 4, 4,0x201c,0x0006, 0, 5,0x1010,divzeroflag,
+ 0,0,&xtensa_mask31,0,0,0)
+ XTREG(260,1092, 1, 4, 4,0x201d,0x0006, 0, 5,0x1010,overflowflag,
+ 0,0,&xtensa_mask32,0,0,0)
+ XTREG(261,1096, 1, 4, 4,0x201e,0x0006, 0, 5,0x1010,underflowflag,
+ 0,0,&xtensa_mask33,0,0,0)
+ XTREG(262,1100, 1, 4, 4,0x201f,0x0006, 0, 5,0x1010,inexactflag,
+ 0,0,&xtensa_mask34,0,0,0)
+ XTREG(263,1104,20, 4, 4,0x2020,0x0006, 0, 5,0x1010,fpreserved20,
+ 0,0,&xtensa_mask35,0,0,0)
+ XTREG(264,1108,20, 4, 4,0x2021,0x0006, 0, 5,0x1010,fpreserved20a,
+ 0,0,&xtensa_mask36,0,0,0)
+ XTREG(265,1112, 5, 4, 4,0x2022,0x0006, 0, 5,0x1010,fpreserved5,
+ 0,0,&xtensa_mask37,0,0,0)
+ XTREG(266,1116, 7, 4, 4,0x2023,0x0006, 0, 5,0x1010,fpreserved7,
+ 0,0,&xtensa_mask38,0,0,0)
+ XTREG(267,1120,40, 8, 4,0x2024,0x0006, 3, 5,0x0210,accx,
+ 0,0,&xtensa_mask39,0,0,0)
+ XTREG(268,1128,160,20, 4,0x2025,0x0006, 3, 5,0x0210,qacc_h,
+ 0,0,&xtensa_mask40,0,0,0)
+ XTREG(269,1148,160,20, 4,0x2026,0x0006, 3, 5,0x0210,qacc_l,
+ 0,0,&xtensa_mask41,0,0,0)
XTREG_END
};
#ifdef XTENSA_CONFIG_INSTANTIATE
-XTENSA_CONFIG_INSTANTIATE(rmap,0)
+XTENSA_CONFIG_INSTANTIATE(rmap,16)
#endif

128
devel/xtensa-esp32s3-elf/gdb/patches/patch-gdb_xtensa-xtregs_c Normal file
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@ -0,0 +1,128 @@
File from espressif overlays.
Index: gdb/xtensa-xtregs.c
--- gdb/xtensa-xtregs.c.orig
+++ gdb/xtensa-xtregs.c
@@ -1,39 +1,94 @@
-/* Table mapping between kernel xtregset and GDB register cache.
- Copyright (C) 2007-2020 Free Software Foundation, Inc.
+/* Customized table mapping between kernel xtregset and GDB register cache.
- This file is part of GDB.
+ Customer ID=15128; Build=0x90f1f; Copyright (c) 2007-2010 Tensilica Inc.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 3 of the
- License, or (at your option) any later version.
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-typedef struct
-{
- int gdb_regnum;
- int gdb_offset;
- int ptrace_cp_offset;
- int ptrace_offset;
- int size;
- int coproc;
- int dbnum;
- const char *name;
-} xtensa_regtable_t;
+typedef struct {
+ int gdb_regnum;
+ int gdb_offset;
+ int ptrace_cp_offset;
+ int ptrace_offset;
+ int size;
+ int coproc;
+ int dbnum;
+ char* name
+;} xtensa_regtable_t;
-#define XTENSA_ELF_XTREG_SIZE 4
+#define XTENSA_ELF_XTREG_SIZE 320
-const xtensa_regtable_t xtensa_regmap_table[] =
-{
+const xtensa_regtable_t xtensa_regmap_table[] = {
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
- { 44, 176, 0, 0, 4, -1, 0x020c, "scompare1" },
+ { 75, 300, 8, 8, 4, -1, 0x0204, "br" },
+ { 76, 304, 12, 12, 4, -1, 0x020c, "scompare1" },
+ { 77, 308, 0, 0, 4, -1, 0x0210, "acclo" },
+ { 78, 312, 4, 4, 4, -1, 0x0211, "acchi" },
+ { 79, 316, 16, 16, 4, -1, 0x0220, "m0" },
+ { 80, 320, 20, 20, 4, -1, 0x0221, "m1" },
+ { 81, 324, 24, 24, 4, -1, 0x0222, "m2" },
+ { 82, 328, 28, 28, 4, -1, 0x0223, "m3" },
+ { 84, 336, 8, 40, 4, 0, 0x0030, "f0" },
+ { 85, 340, 12, 44, 4, 0, 0x0031, "f1" },
+ { 86, 344, 16, 48, 4, 0, 0x0032, "f2" },
+ { 87, 348, 20, 52, 4, 0, 0x0033, "f3" },
+ { 88, 352, 24, 56, 4, 0, 0x0034, "f4" },
+ { 89, 356, 28, 60, 4, 0, 0x0035, "f5" },
+ { 90, 360, 32, 64, 4, 0, 0x0036, "f6" },
+ { 91, 364, 36, 68, 4, 0, 0x0037, "f7" },
+ { 92, 368, 40, 72, 4, 0, 0x0038, "f8" },
+ { 93, 372, 44, 76, 4, 0, 0x0039, "f9" },
+ { 94, 376, 48, 80, 4, 0, 0x003a, "f10" },
+ { 95, 380, 52, 84, 4, 0, 0x003b, "f11" },
+ { 96, 384, 56, 88, 4, 0, 0x003c, "f12" },
+ { 97, 388, 60, 92, 4, 0, 0x003d, "f13" },
+ { 98, 392, 64, 96, 4, 0, 0x003e, "f14" },
+ { 99, 396, 68, 100, 4, 0, 0x003f, "f15" },
+ { 100, 400, 0, 32, 4, 0, 0x03e8, "fcr" },
+ { 101, 404, 4, 36, 4, 0, 0x03e9, "fsr" },
+ { 102, 408, 0, 112, 4, 3, 0x0300, "accx_0" },
+ { 103, 412, 4, 116, 4, 3, 0x0301, "accx_1" },
+ { 104, 416, 8, 120, 4, 3, 0x0302, "qacc_h_0" },
+ { 105, 420, 12, 124, 4, 3, 0x0303, "qacc_h_1" },
+ { 106, 424, 16, 128, 4, 3, 0x0304, "qacc_h_2" },
+ { 107, 428, 20, 132, 4, 3, 0x0305, "qacc_h_3" },
+ { 108, 432, 24, 136, 4, 3, 0x0306, "qacc_h_4" },
+ { 109, 436, 28, 140, 4, 3, 0x0307, "qacc_l_0" },
+ { 110, 440, 32, 144, 4, 3, 0x0308, "qacc_l_1" },
+ { 111, 444, 36, 148, 4, 3, 0x0309, "qacc_l_2" },
+ { 112, 448, 40, 152, 4, 3, 0x030a, "qacc_l_3" },
+ { 113, 452, 44, 156, 4, 3, 0x030b, "qacc_l_4" },
+ { 114, 456, 48, 160, 4, 3, 0x030d, "sar_byte" },
+ { 115, 460, 52, 164, 4, 3, 0x030e, "fft_bit_width" },
+ { 116, 464, 56, 168, 4, 3, 0x030f, "ua_state_0" },
+ { 117, 468, 60, 172, 4, 3, 0x0310, "ua_state_1" },
+ { 118, 472, 64, 176, 4, 3, 0x0311, "ua_state_2" },
+ { 119, 476, 68, 180, 4, 3, 0x0312, "ua_state_3" },
+ { 120, 480, 80, 192, 16, 3, 0x1008, "q0" },
+ { 121, 496, 96, 208, 16, 3, 0x1009, "q1" },
+ { 122, 512, 112, 224, 16, 3, 0x100a, "q2" },
+ { 123, 528, 128, 240, 16, 3, 0x100b, "q3" },
+ { 124, 544, 144, 256, 16, 3, 0x100c, "q4" },
+ { 125, 560, 160, 272, 16, 3, 0x100d, "q5" },
+ { 126, 576, 176, 288, 16, 3, 0x100e, "q6" },
+ { 127, 592, 192, 304, 16, 3, 0x100f, "q7" },
{ 0 }
};
+

156
devel/xtensa-esp32s3-elf/gdb/patches/patch-include_xtensa-config_h Normal file
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@ -0,0 +1,156 @@
xtensa-config.h file for ESP32
Index: include/xtensa-config.h
--- include/xtensa-config.h.orig
+++ include/xtensa-config.h
@@ -1,5 +1,6 @@
/* Xtensa configuration settings.
- Copyright (C) 2001-2019 Free Software Foundation, Inc.
+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+ Free Software Foundation, Inc.
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
This program is free software; you can redistribute it and/or modify
@@ -25,7 +26,7 @@
macros. */
#undef XCHAL_HAVE_BE
-#define XCHAL_HAVE_BE 1
+#define XCHAL_HAVE_BE 0
#undef XCHAL_HAVE_DENSITY
#define XCHAL_HAVE_DENSITY 1
@@ -49,7 +50,7 @@
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#undef XCHAL_HAVE_MAC16
-#define XCHAL_HAVE_MAC16 0
+#define XCHAL_HAVE_MAC16 1
#undef XCHAL_HAVE_MUL16
#define XCHAL_HAVE_MUL16 1
@@ -58,7 +59,7 @@
#define XCHAL_HAVE_MUL32 1
#undef XCHAL_HAVE_MUL32_HIGH
-#define XCHAL_HAVE_MUL32_HIGH 0
+#define XCHAL_HAVE_MUL32_HIGH 1
#undef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 1
@@ -85,30 +86,37 @@
#define XCHAL_HAVE_S32C1I 1
#undef XCHAL_HAVE_BOOLEANS
-#define XCHAL_HAVE_BOOLEANS 0
+#define XCHAL_HAVE_BOOLEANS 1
#undef XCHAL_HAVE_FP
-#define XCHAL_HAVE_FP 0
+#define XCHAL_HAVE_FP 1
#undef XCHAL_HAVE_FP_DIV
-#define XCHAL_HAVE_FP_DIV 0
+#define XCHAL_HAVE_FP_DIV 1
#undef XCHAL_HAVE_FP_RECIP
-#define XCHAL_HAVE_FP_RECIP 0
+#define XCHAL_HAVE_FP_RECIP 1
#undef XCHAL_HAVE_FP_SQRT
-#define XCHAL_HAVE_FP_SQRT 0
+#define XCHAL_HAVE_FP_SQRT 1
#undef XCHAL_HAVE_FP_RSQRT
-#define XCHAL_HAVE_FP_RSQRT 0
+#define XCHAL_HAVE_FP_RSQRT 1
+#undef XCHAL_HAVE_FP_POSTINC
+#define XCHAL_HAVE_FP_POSTINC 1
+
+#undef XCHAL_HAVE_DFP_ACCEL
+#define XCHAL_HAVE_DFP_ACCEL 0
+/* For backward compatibility */
#undef XCHAL_HAVE_DFP_accel
-#define XCHAL_HAVE_DFP_accel 0
+#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
+
#undef XCHAL_HAVE_WINDOWED
#define XCHAL_HAVE_WINDOWED 1
#undef XCHAL_NUM_AREGS
-#define XCHAL_NUM_AREGS 32
+#define XCHAL_NUM_AREGS 64
#undef XCHAL_HAVE_WIDE_BRANCHES
#define XCHAL_HAVE_WIDE_BRANCHES 0
@@ -118,34 +126,31 @@
#undef XCHAL_ICACHE_SIZE
-#define XCHAL_ICACHE_SIZE 16384
+#define XCHAL_ICACHE_SIZE 0
#undef XCHAL_DCACHE_SIZE
-#define XCHAL_DCACHE_SIZE 16384
+#define XCHAL_DCACHE_SIZE 0
#undef XCHAL_ICACHE_LINESIZE
-#define XCHAL_ICACHE_LINESIZE 32
+#define XCHAL_ICACHE_LINESIZE 16
#undef XCHAL_DCACHE_LINESIZE
-#define XCHAL_DCACHE_LINESIZE 32
+#define XCHAL_DCACHE_LINESIZE 16
#undef XCHAL_ICACHE_LINEWIDTH
-#define XCHAL_ICACHE_LINEWIDTH 5
+#define XCHAL_ICACHE_LINEWIDTH 4
#undef XCHAL_DCACHE_LINEWIDTH
-#define XCHAL_DCACHE_LINEWIDTH 5
+#define XCHAL_DCACHE_LINEWIDTH 4
#undef XCHAL_DCACHE_IS_WRITEBACK
-#define XCHAL_DCACHE_IS_WRITEBACK 1
+#define XCHAL_DCACHE_IS_WRITEBACK 0
#undef XCHAL_HAVE_MMU
-#define XCHAL_HAVE_MMU 1
+#define XCHAL_HAVE_MMU 0
-#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
-
#undef XCHAL_HAVE_DEBUG
#define XCHAL_HAVE_DEBUG 1
@@ -160,7 +165,7 @@
#undef XCHAL_MAX_INSTRUCTION_SIZE
-#define XCHAL_MAX_INSTRUCTION_SIZE 3
+#define XCHAL_MAX_INSTRUCTION_SIZE 4
#undef XCHAL_INST_FETCH_WIDTH
#define XCHAL_INST_FETCH_WIDTH 4
@@ -172,5 +177,16 @@
#define XSHAL_ABI XTHAL_ABI_WINDOWED
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
+
+
+#undef XCHAL_M_STAGE
+#define XCHAL_M_STAGE 2
+
+#undef XTENSA_MARCH_LATEST
+#define XTENSA_MARCH_LATEST 270012
+
+#undef XTENSA_MARCH_EARLIEST
+#define XTENSA_MARCH_EARLIEST 270012
+
#endif /* !XTENSA_CONFIG_H */

1
devel/xtensa-esp32s3-elf/gdb/pkg/DESCR Normal file
View File

@ -0,0 +1 @@
GNU debugger, configured for the xtensa-esp32s3-elf target.

45
devel/xtensa-esp32s3-elf/gdb/pkg/PLIST Normal file
View File

@ -0,0 +1,45 @@
xtensa-esp32s3-elf/
xtensa-esp32s3-elf/bin/
@bin xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-gdb
xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-gdb-add-index
xtensa-esp32s3-elf/include/
xtensa-esp32s3-elf/include/gdb/
xtensa-esp32s3-elf/include/gdb/jit-reader.h
xtensa-esp32s3-elf/lib/
xtensa-esp32s3-elf/lib/charset.alias
xtensa-esp32s3-elf/share/
xtensa-esp32s3-elf/share/gdb/
xtensa-esp32s3-elf/share/gdb/syscalls/
xtensa-esp32s3-elf/share/gdb/syscalls/aarch64-linux.xml
xtensa-esp32s3-elf/share/gdb/syscalls/amd64-linux.xml
xtensa-esp32s3-elf/share/gdb/syscalls/arm-linux.xml
xtensa-esp32s3-elf/share/gdb/syscalls/freebsd.xml
xtensa-esp32s3-elf/share/gdb/syscalls/gdb-syscalls.dtd
xtensa-esp32s3-elf/share/gdb/syscalls/i386-linux.xml
xtensa-esp32s3-elf/share/gdb/syscalls/mips-n32-linux.xml
xtensa-esp32s3-elf/share/gdb/syscalls/mips-n64-linux.xml
xtensa-esp32s3-elf/share/gdb/syscalls/mips-o32-linux.xml
xtensa-esp32s3-elf/share/gdb/syscalls/ppc-linux.xml
xtensa-esp32s3-elf/share/gdb/syscalls/ppc64-linux.xml
xtensa-esp32s3-elf/share/gdb/syscalls/s390-linux.xml
xtensa-esp32s3-elf/share/gdb/syscalls/s390x-linux.xml
xtensa-esp32s3-elf/share/gdb/syscalls/sparc-linux.xml
xtensa-esp32s3-elf/share/gdb/syscalls/sparc64-linux.xml
xtensa-esp32s3-elf/share/gdb/system-gdbinit/
xtensa-esp32s3-elf/share/gdb/system-gdbinit/elinos.py
xtensa-esp32s3-elf/share/gdb/system-gdbinit/wrs-linux.py
@info xtensa-esp32s3-elf/share/info/
@info xtensa-esp32s3-elf/share/info/annotate.info
@comment @info xtensa-esp32s3-elf/share/info/bfd.info
@info xtensa-esp32s3-elf/share/info/gdb.info
@info xtensa-esp32s3-elf/share/info/stabs.info
@mandir xtensa-esp32s3-elf/share/man/
xtensa-esp32s3-elf/share/man/man1/
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-gdb-add-index.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-gdb.1
@man xtensa-esp32s3-elf/share/man/man1/xtensa-esp32s3-elf-gdbserver.1
xtensa-esp32s3-elf/share/man/man5/
@man xtensa-esp32s3-elf/share/man/man5/xtensa-esp32s3-elf-gdbinit.5
xtensa-esp32s3-elf/xtensa-esp32s3-elf/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/libiberty.a

39
devel/xtensa-esp32s3-elf/newlib/Makefile Normal file
View File

@ -0,0 +1,39 @@
COMMENT = newlib for ${CONFIG} cross-development
VERSION = 2021.2
PKGNAME = ${CONFIG}-newlib-${VERSION}
GH_ACCOUNT = espressif
GH_PROJECT = newlib-esp32
GH_TAGNAME = esp-2021r2
BUILD_DEPENDS = devel/${CONFIG}/binutils \
devel/${CONFIG}/gcc-bootstrap
RUN_DEPENDS = devel/${CONFIG}/binutils
USE_GROFF = No
CONFIGURE_ENV = CC_FOR_TARGET="${INSTALLDIR}/bootstrap/bin/${CONFIG}-gcc" \
AR_FOR_TARGET="${INSTALLDIR}/bin/${CONFIG}-ar" \
RANLIB_FOR_TARGET="${INSTALLDIR}/bin/${CONFIG}-ranlib"
CONFIGURE_ARGS += --enable-multilib \
--enable-newlib-io-float \
--disable-newlib-io-long-double \
--enable-newlib-io-pos-args \
--enable-newlib-io-c99-formats \
--enable-newlib-io-long-long \
--disable-newlib-register-fini \
--disable-newlib-nano-formatted-io \
--disable-newlib-supplied-syscalls \
--enable-newlib-atexit-dynamic-alloc \
--disable-newlib-global-atexit \
--disable-lite-exit \
--enable-newlib-reent-small \
--enable-newlib-multithread \
--enable-newlib-wide-orient \
--enable-newlib-unbuf-stream-opt \
--enable-target-optspace \
--enable-newlib-nano-malloc
.include <bsd.port.mk>

2
devel/xtensa-esp32s3-elf/newlib/distinfo Normal file
View File

@ -0,0 +1,2 @@
SHA256 (newlib-esp32-esp-2021r2.tar.gz) = 2uh6DdEM1PEHmAqTzUWJQK4C0+A+/bTTSJufusqfR44=
SIZE (newlib-esp32-esp-2021r2.tar.gz) = 21919193

398
devel/xtensa-esp32s3-elf/newlib/patches/patch-newlib_libc_sys_xtensa_include_xtensa_config_core-isa_h Normal file
View File

@ -0,0 +1,398 @@
Index: newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h
--- newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h.orig
+++ newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h
@@ -7,7 +7,7 @@
/* Xtensa processor core configuration information.
- Copyright (c) 1999-2016 Tensilica Inc.
+ Copyright (c) 1999-2021 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
@@ -50,7 +50,7 @@
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
+#define XCHAL_MAX_INSTRUCTION_SIZE 4 /* max instr bytes (3..8) */
#define XCHAL_HAVE_DEBUG 1 /* debug option */
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
@@ -68,6 +68,7 @@
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
@@ -95,48 +96,68 @@
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
-#define XCHAL_HAVE_FUSION 0 /* Fusion*/
-#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
+#define XCHAL_HAVE_FUSION 0 /* Fusion*/
+#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
+#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
+#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
+#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
+#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
+#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
+#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
+#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
+#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
+#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */
+#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */
+#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
#define XCHAL_HAVE_HIFI_MINI 0
-#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
-#define XCHAL_HAVE_FP 1 /* single prec floating point */
-#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
+#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
+#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */
+#define XCHAL_HAVE_FP 1 /* single prec floating point */
+#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
+#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
+#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
+#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
+#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
+#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
+#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
+#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
+#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
+#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
+#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
+
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
-#define XCHAL_HAVE_PDX4 0 /* PDX4 */
+
+#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
+#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
+#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */
+#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
+#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
+#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
+
+#define XCHAL_HAVE_PDX 0 /* PDX */
+#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
+#define XCHAL_HAVE_PDX4 0 /* PDX4 */
+#define XCHAL_HAVE_PDX8 0 /* PDX8 */
+#define XCHAL_HAVE_PDX16 0 /* PDX16 */
+
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
@@ -144,6 +165,7 @@
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
+#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
@@ -151,10 +173,19 @@
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
+#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
+#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
+#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
+#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */
+#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
+#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
+#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */
+#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */
+#define XCHAL_HAVE_VISIONC 0 /* Vision C */
+
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
@@ -162,8 +193,8 @@
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay
+#define XCHAL_DATA_WIDTH 16 /* data width in bytes */
+#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
(1 = 5-stage, 2 = 7-stage) */
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
@@ -173,34 +204,34 @@
#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
-#define XCHAL_SW_VERSION 1100003 /* sw version of this header */
+#define XCHAL_SW_VERSION 1200012 /* sw version of this header */
-#define XCHAL_CORE_ID "esp32_v3_49_prod" /* alphanum core name
+#define XCHAL_CORE_ID "LX7_ESP32_S3_MP" /* alphanum core name
(CoreID) set in the Xtensa
Processor Generator */
-#define XCHAL_BUILD_UNIQUE_ID 0x0005FE96 /* 22-bit sw build ID */
+#define XCHAL_BUILD_UNIQUE_ID 0x00090F1F /* 22-bit sw build ID */
/*
* These definitions describe the hardware targeted by this software.
*/
-#define XCHAL_HW_CONFIGID0 0xC2BCFFFE /* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1 0x1CC5FE96 /* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */
-#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION 260003 /* major*100+minor */
-#define XCHAL_HW_REL_LX6 1
-#define XCHAL_HW_REL_LX6_0 1
-#define XCHAL_HW_REL_LX6_0_3 1
+#define XCHAL_HW_CONFIGID0 0xC2F0FFFE /* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1 0x23090F1F /* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME "LX7.0.12" /* full version name */
+#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR 12 /* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION 270012 /* major*100+minor */
+#define XCHAL_HW_REL_LX7 1
+#define XCHAL_HW_REL_LX7_0 1
+#define XCHAL_HW_REL_LX7_0_12 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/* If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */
+#define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR 12 /* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION 270012 /* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR 12 /* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION 270012 /* latest targeted hw */
/*----------------------------------------------------------------------
@@ -208,9 +239,9 @@
----------------------------------------------------------------------*/
#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */
#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */
#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
@@ -243,11 +274,14 @@
CACHE
----------------------------------------------------------------------*/
-#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
+#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
+
#define XCHAL_HAVE_AXI 0 /* AXI bus */
+#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
+#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */
+#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
@@ -264,6 +298,8 @@
#define XCHAL_DCACHE_LINE_LOCKABLE 0
#define XCHAL_ICACHE_ECC_PARITY 0
#define XCHAL_DCACHE_ECC_PARITY 0
+#define XCHAL_ICACHE_ECC_WIDTH 1
+#define XCHAL_DCACHE_ECC_WIDTH 1
/* Cache access size in bytes (affects operation of SICW instruction): */
#define XCHAL_ICACHE_ACCESS_SIZE 1
@@ -278,59 +314,33 @@
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */
-#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
+#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
+#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
+#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
-/* Instruction ROM 0: */
-#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */
-#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */
-#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */
-#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
-
/* Instruction RAM 0: */
#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
-#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */
+#define XCHAL_INSTRAM0_SIZE 67108864 /* size in bytes */
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
+#define XCHAL_HAVE_INSTRAM0 1
+#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
-/* Instruction RAM 1: */
-#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */
-#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */
-#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */
-#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
-
-/* Data ROM 0: */
-#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */
-#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */
-#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */
-#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
-#define XCHAL_DATAROM0_BANKS 1 /* number of banks */
-
/* Data RAM 0: */
-#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */
-#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */
-#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */
+#define XCHAL_DATARAM0_VADDR 0x3C000000 /* virtual address */
+#define XCHAL_DATARAM0_PADDR 0x3C000000 /* physical address */
+#define XCHAL_DATARAM0_SIZE 67108864 /* size in bytes */
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
+#define XCHAL_HAVE_DATARAM0 1
+#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
-/* Data RAM 1: */
-#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */
-#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */
-#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */
-#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
-#define XCHAL_DATARAM1_BANKS 1 /* number of banks */
+#define XCHAL_HAVE_IDMA 0
+#define XCHAL_HAVE_IDMA_TRANSPOSE 0
-/* XLMI Port 0: */
-#define XCHAL_XLMI0_VADDR 0x3FF00000 /* virtual address */
-#define XCHAL_XLMI0_PADDR 0x3FF00000 /* physical address */
-#define XCHAL_XLMI0_SIZE 524288 /* size in bytes */
-#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
-
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
@@ -450,6 +460,9 @@
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800
+#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
+#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
+#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
/* Interrupt numbers assigned to specific interrupt sources: */
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
@@ -457,7 +470,7 @@
#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
-#define XCHAL_PROFILING_INTERRUPT 11 /* profiling interrupt */
+#define XCHAL_PROFILING_INTERRUPT 11
/* Interrupt numbers for levels at which only one interrupt is configured: */
#define XCHAL_INTLEVEL7_NUM 14
@@ -605,7 +618,7 @@
/* Misc */
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */
+#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
/* On-Chip Debug (OCD) */
@@ -619,7 +632,7 @@
#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */
#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */
+#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
/* Perf counters */
@@ -642,11 +655,25 @@
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
[autorefill] and protection)
usable for an MMU-based OS */
-/* If none of the above last 4 are set, it's a custom TLB configuration. */
+/* If none of the above last 5 are set, it's a custom TLB configuration. */
+
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
+
+/*----------------------------------------------------------------------
+ MPU
+ ----------------------------------------------------------------------*/
+#define XCHAL_HAVE_MPU 0
+#define XCHAL_MPU_ENTRIES 0
+
+#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
+#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
+#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
+
+#define XCHAL_MPU_ALIGN_BITS 0
+#define XCHAL_MPU_ALIGN 0
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */

5
devel/xtensa-esp32s3-elf/newlib/pkg/DESCR Normal file
View File

@ -0,0 +1,5 @@
Newlib is a C library intended for use on embedded systems. It is a
conglomeration of several library parts, all under free software
licenses that make them easily usable on embedded products.
This port has been configured for the xtensa-esp32s3-elf target.

180
devel/xtensa-esp32s3-elf/newlib/pkg/PLIST Normal file
View File

@ -0,0 +1,180 @@
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/_ansi.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/_newlib_version.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/_syslist.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/alloca.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/ar.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/argz.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/assert.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/bits/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/complex.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/config.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/cpio.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/ctype.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/devctl.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/dirent.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/elf.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/envlock.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/envz.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/errno.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/fastmath.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/fcntl.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/fenv.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/fnmatch.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/getopt.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/glob.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/grp.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/iconv.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/ieeefp.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/inttypes.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/langinfo.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/libgen.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/limits.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/locale.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/_arc4random.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/_default_types.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/_endian.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/_time.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/_types.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/ansi.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/endian.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/fastmath.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/ieeefp.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/malloc.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/param.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/setjmp-dj.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/setjmp.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/stdlib.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/termios.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/time.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/machine/types.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/malloc.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/math.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/memory.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/ndbm.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/newlib.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/paths.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/pthread.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/pwd.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/reent.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/regdef.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/regex.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/rpc/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sched.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/search.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/setjmp.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/signal.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/spawn.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/ssp/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/ssp/ssp.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/ssp/stdio.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/ssp/stdlib.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/ssp/string.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/ssp/strings.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/ssp/unistd.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/ssp/wchar.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/stdatomic.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/stdint.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/stdio.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/stdio_ext.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/stdlib.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/string.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/strings.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/_default_fcntl.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/_intsup.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/_locale.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/_pthreadtypes.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/_sigset.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/_stdint.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/_timespec.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/_timeval.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/_types.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/cdefs.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/config.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/custom_file.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/dir.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/dirent.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/errno.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/fcntl.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/features.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/fenv.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/file.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/iconvnls.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/lock.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/param.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/queue.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/reent.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/resource.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/sched.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/select.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/signal.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/stat.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/stdio.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/string.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/syslimits.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/time.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/timeb.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/times.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/timespec.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/tree.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/types.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/unistd.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/utime.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/sys/wait.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/tar.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/termios.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/tgmath.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/threads.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/time.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/unctrl.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/unistd.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/utime.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/utmp.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/wchar.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/wctype.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/wordexp.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/xtensa/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/xtensa/config/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/include/xtensa/config/core-isa.h
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/crt0.o
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/default.specs
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/crt0.o
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/default.specs
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/libc.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/libg.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/libgloss.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/libm.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/libnosys.a
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/nano.specs
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/no-rtti/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/no-rtti/crt0.o
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/no-rtti/default.specs
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/no-rtti/libc.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/no-rtti/libg.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/no-rtti/libgloss.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/no-rtti/libm.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/no-rtti/libnosys.a
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/no-rtti/nano.specs
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/no-rtti/nosys.specs
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/esp32-psram/nosys.specs
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/libc.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/libg.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/libgloss.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/libm.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/libnosys.a
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/nano.specs
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/no-rtti/
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/no-rtti/crt0.o
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/no-rtti/default.specs
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/no-rtti/libc.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/no-rtti/libg.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/no-rtti/libgloss.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/no-rtti/libm.a
@static-lib xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/no-rtti/libnosys.a
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/no-rtti/nano.specs
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/no-rtti/nosys.specs
xtensa-esp32s3-elf/xtensa-esp32s3-elf/lib/nosys.specs