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r236042
Sparc: Add alternate aliases for conditional branch instructions.

r236107
Sparc: Prefer reg+reg address encoding when only one register used.

r236137
Make Sparc assembler accept parenthesized constant expressions.

from brad (maintainer)
This commit is contained in:
ajacoutot 2015-05-11 23:21:51 +00:00
parent fe9bf95b16
commit 9b0b92263c
3 changed files with 98 additions and 22 deletions
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4
devel/llvm/Makefile
View File

@ -1,4 +1,4 @@
# $OpenBSD: Makefile,v 1.101 2015/04/09 22:25:02 sthen Exp $
# $OpenBSD: Makefile,v 1.102 2015/05/11 23:21:51 ajacoutot Exp $
# XXX: Remember to bump MODCLANG_VERSION in lang/clang/clang.port.mk when
# updating this port.
@ -10,7 +10,7 @@ COMMENT = modular, fast C/C++/ObjC compiler, static analyzer and tools
LLVM_V = 3.5
DISTNAME = llvm-${LLVM_V}.20140228
REVISION = 28
REVISION = 29
CATEGORIES = devel
MASTER_SITES = http://comstyle.com/source/
EXTRACT_SUFX = .tar.xz

74
devel/llvm/patches/patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp
View File

@ -1,9 +1,20 @@
$OpenBSD: patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp,v 1.1 2014/07/11 01:05:24 brad Exp $
$OpenBSD: patch-lib_Target_Sparc_AsmParser_SparcAsmParser_cpp,v 1.2 2015/05/11 23:21:51 ajacoutot Exp $
Sync up the SPARC backend up to commit r203424.
--- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp.orig Sun Jun 15 02:46:35 2014
+++ lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Sun Jun 15 03:00:25 2014
r236107
Sparc: Prefer reg+reg address encoding when only one register used.
Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces.
Futhermore, reg+imm is invalid for the (not yet supported) "alternate
address space" instructions.
r236137
Make Sparc assembler accept parenthesized constant expressions.
--- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp.orig Sun Mar 2 21:57:39 2014
+++ lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Thu Apr 30 02:49:39 2015
@@ -12,9 +12,11 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/MC/MCContext.h"
@ -37,7 +48,25 @@ Sync up the SPARC backend up to commit r203424.
public:
SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII)
@@ -415,7 +422,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
@@ -354,13 +361,11 @@ class SparcOperand : public MCParsedAsmOperand { (publ
return Op;
}
- static SparcOperand *CreateMEMri(unsigned Base,
- const MCExpr *Off,
- SMLoc S, SMLoc E) {
- SparcOperand *Op = new SparcOperand(k_MemoryImm);
+ static SparcOperand *CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
+ SparcOperand *Op = new SparcOperand(k_MemoryReg);
Op->Mem.Base = Base;
- Op->Mem.OffsetReg = 0;
- Op->Mem.Off = Off;
+ Op->Mem.OffsetReg = Sparc::G0; // always 0
+ Op->Mem.Off = 0;
Op->StartLoc = S;
Op->EndLoc = E;
return Op;
@@ -415,7 +420,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return Error(ErrorLoc, "invalid operand for instruction");
}
case Match_MnemonicFail:
@ -46,7 +75,7 @@ Sync up the SPARC backend up to commit r203424.
}
return true;
}
@@ -439,21 +446,30 @@ ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc
@@ -439,21 +444,30 @@ ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc
return Error(StartLoc, "invalid register name");
}
@ -82,7 +111,7 @@ Sync up the SPARC backend up to commit r203424.
if (parseOperand(Operands, Name) != MatchOperand_Success) {
SMLoc Loc = getLexer().getLoc();
Parser.eatToEndOfStatement();
@@ -482,8 +498,52 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef
@@ -482,8 +496,52 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef
bool SparcAsmParser::
ParseDirective(AsmToken DirectiveID)
{
@ -137,7 +166,16 @@ Sync up the SPARC backend up to commit r203424.
return false;
}
@@ -577,7 +637,8 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Ope
@@ -504,7 +562,7 @@ parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &
case AsmToken::Comma:
case AsmToken::RBrac:
case AsmToken::EndOfStatement:
- Operands.push_back(SparcOperand::CreateMEMri(BaseReg, 0, S, E));
+ Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
return MatchOperand_Success;
case AsmToken:: Plus:
@@ -577,7 +635,8 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Ope
}
SparcOperand *Op = 0;
@ -147,7 +185,7 @@ Sync up the SPARC backend up to commit r203424.
if (ResTy != MatchOperand_Success || !Op)
return MatchOperand_ParseFail;
@@ -588,7 +649,7 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Ope
@@ -588,7 +647,7 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Ope
}
SparcAsmParser::OperandMatchResultTy
@ -156,7 +194,7 @@ Sync up the SPARC backend up to commit r203424.
{
SMLoc S = Parser.getTok().getLoc();
@@ -621,11 +682,6 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
@@ -621,11 +680,6 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
else
Op = SparcOperand::CreateToken("%icc", S);
break;
@ -168,7 +206,15 @@ Sync up the SPARC backend up to commit r203424.
}
break;
}
@@ -649,6 +705,10 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
@@ -637,6 +691,7 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
case AsmToken::Minus:
case AsmToken::Integer:
+ case AsmToken::LParen:
if (!getParser().parseExpression(EVal, E))
Op = SparcOperand::CreateImm(EVal, S, E);
break;
@@ -649,6 +704,10 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
getContext());
@ -179,7 +225,7 @@ Sync up the SPARC backend up to commit r203424.
Op = SparcOperand::CreateImm(Res, S, E);
}
break;
@@ -657,6 +717,27 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
@@ -657,6 +716,27 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op
return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
}
@ -207,7 +253,7 @@ Sync up the SPARC backend up to commit r203424.
bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
unsigned &RegNo,
unsigned &RegKind)
@@ -704,7 +785,7 @@ bool SparcAsmParser::matchRegisterName(const AsmToken
@@ -704,7 +784,7 @@ bool SparcAsmParser::matchRegisterName(const AsmToken
&& !name.substr(3).getAsInteger(10, intVal)
&& intVal < 4) {
// FIXME: check 64bit and handle %fcc1 - %fcc3
@ -216,7 +262,7 @@ Sync up the SPARC backend up to commit r203424.
RegKind = SparcOperand::rk_CCReg;
return true;
}
@@ -767,7 +848,32 @@ bool SparcAsmParser::matchRegisterName(const AsmToken
@@ -767,7 +847,32 @@ bool SparcAsmParser::matchRegisterName(const AsmToken
return false;
}
@ -249,7 +295,7 @@ Sync up the SPARC backend up to commit r203424.
bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
SMLoc &EndLoc)
{
@@ -790,6 +896,23 @@ bool SparcAsmParser::matchSparcAsmModifiers(const MCEx
@@ -790,6 +895,23 @@ bool SparcAsmParser::matchSparcAsmModifiers(const MCEx
const MCExpr *subExpr;
if (Parser.parseParenExpression(subExpr, EndLoc))
return false;

42
devel/llvm/patches/patch-lib_Target_Sparc_SparcInstrAliases_td
View File

@ -1,4 +1,4 @@
$OpenBSD: patch-lib_Target_Sparc_SparcInstrAliases_td,v 1.2 2014/09/18 20:19:27 brad Exp $
$OpenBSD: patch-lib_Target_Sparc_SparcInstrAliases_td,v 1.3 2015/05/11 23:21:51 ajacoutot Exp $
Sync up the SPARC backend up to commit r203424.
@ -8,8 +8,11 @@ Sparc: disable printing of jmp/call aliases (C++ does it)
These aliases are handled entirely in C++ and only having TableGen InstAliases
for some of them was confusing LLVM.
r236042
Sparc: Add alternate aliases for conditional branch instructions.
--- lib/Target/Sparc/SparcInstrAliases.td.orig Sun Mar 2 21:57:39 2014
+++ lib/Target/Sparc/SparcInstrAliases.td Mon Sep 15 15:27:10 2014
+++ lib/Target/Sparc/SparcInstrAliases.td Wed Apr 29 20:22:04 2015
@@ -13,32 +13,53 @@
// Instruction aliases for conditional moves.
@ -196,7 +199,7 @@ for some of them was confusing LLVM.
}
@@ -76,13 +199,48 @@ multiclass fp_cond_alias<string cond, int condVal> {
@@ -76,20 +199,57 @@ multiclass fp_cond_alias<string cond, int condVal> {
def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
(FBCOND brtarget:$imm, condVal), 0>;
@ -250,7 +253,24 @@ for some of them was confusing LLVM.
Requires<[HasV9, HasHardQuad]>;
}
@@ -103,6 +261,8 @@ defm : int_cond_alias<"neg", 0b0110>;
defm : int_cond_alias<"a", 0b1000>;
defm : int_cond_alias<"n", 0b0000>;
defm : int_cond_alias<"ne", 0b1001>;
+defm : int_cond_alias<"nz", 0b1001>; // same as ne
defm : int_cond_alias<"e", 0b0001>;
+defm : int_cond_alias<"z", 0b0001>; // same as e
defm : int_cond_alias<"g", 0b1010>;
defm : int_cond_alias<"le", 0b0010>;
defm : int_cond_alias<"ge", 0b1011>;
@@ -97,12 +257,16 @@ defm : int_cond_alias<"l", 0b0011>;
defm : int_cond_alias<"gu", 0b1100>;
defm : int_cond_alias<"leu", 0b0100>;
defm : int_cond_alias<"cc", 0b1101>;
+defm : int_cond_alias<"geu", 0b1101>; // same as cc
defm : int_cond_alias<"cs", 0b0101>;
+defm : int_cond_alias<"lu", 0b0101>; // same as cs
defm : int_cond_alias<"pos", 0b1110>;
defm : int_cond_alias<"neg", 0b0110>;
defm : int_cond_alias<"vc", 0b1111>;
defm : int_cond_alias<"vs", 0b0111>;
@ -259,7 +279,17 @@ for some of them was confusing LLVM.
defm : fp_cond_alias<"u", 0b0111>;
defm : fp_cond_alias<"g", 0b0110>;
defm : fp_cond_alias<"ug", 0b0101>;
@@ -118,16 +278,15 @@ defm : fp_cond_alias<"le", 0b1101>;
@@ -110,7 +274,9 @@ defm : fp_cond_alias<"l", 0b0100>;
defm : fp_cond_alias<"ul", 0b0011>;
defm : fp_cond_alias<"lg", 0b0010>;
defm : fp_cond_alias<"ne", 0b0001>;
+defm : fp_cond_alias<"nz", 0b0001>; // same as ne
defm : fp_cond_alias<"e", 0b1001>;
+defm : fp_cond_alias<"z", 0b1001>; // same as e
defm : fp_cond_alias<"ue", 0b1010>;
defm : fp_cond_alias<"ge", 0b1011>;
defm : fp_cond_alias<"uge", 0b1100>;
@@ -118,16 +284,15 @@ defm : fp_cond_alias<"le", 0b1101>;
defm : fp_cond_alias<"ule", 0b1110>;
defm : fp_cond_alias<"o", 0b1111>;
@ -280,7 +310,7 @@ for some of them was confusing LLVM.
// retl -> RETL 8
def : InstAlias<"retl", (RETL 8)>;
@@ -140,3 +299,27 @@ def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0
@@ -140,3 +305,27 @@ def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0
// mov simm13, rd -> or %g0, simm13, rd
def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;