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r223708

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[PowerPC] Don't use a non-allocatable register to implement the 'cc' alias
This commit is contained in:
brad 2014-12-30 22:41:09 +00:00
parent 1693272b86
commit 5189bb6550
3 changed files with 32 additions and 46 deletions
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4
devel/llvm/Makefile
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@ -1,4 +1,4 @@
# $OpenBSD: Makefile,v 1.96 2014/12/30 22:25:47 brad Exp $
# $OpenBSD: Makefile,v 1.97 2014/12/30 22:41:09 brad Exp $
# XXX: Remember to bump MODCLANG_VERSION in lang/clang/clang.port.mk when
# updating this port.
@ -10,7 +10,7 @@ COMMENT = modular, fast C/C++/ObjC compiler, static analyzer and tools
LLVM_V = 3.5
DISTNAME = llvm-${LLVM_V}.20140228
REVISION = 23
REVISION = 24
CATEGORIES = devel
MASTER_SITES = http://comstyle.com/source/
EXTRACT_SUFX = .tar.xz

32
devel/llvm/patches/patch-lib_Target_PowerPC_PPCISelLowering_cpp
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@ -1,4 +1,4 @@
$OpenBSD: patch-lib_Target_PowerPC_PPCISelLowering_cpp,v 1.1 2014/09/11 17:54:13 brad Exp $
$OpenBSD: patch-lib_Target_PowerPC_PPCISelLowering_cpp,v 1.2 2014/12/30 22:41:09 brad Exp $
r213899
Don't use 128bit functions on PPC32.
@ -13,8 +13,23 @@ backend.
r213960
[PowerPC] Support TLS on PPC32/ELF
r223708
[PowerPC] Don't use a non-allocatable register to implement the 'cc' alias
GCC accepts 'cc' as an alias for 'cr0', and we need to do the same when
processing inline asm constraints. This had previously been implemented using a
non-allocatable register, named 'cc', that was listed as an alias of 'cr0', but
the infrastructure does not seem to support this properly (neither the register
allocator nor the scheduler properly accounts for the alias). Instead, we can
just process this as a naming alias inside of the inline asm
constraint-processing code, so we'll do that instead.
There are two regression tests, one where the post-RA scheduler did the wrong
thing with the non-allocatable alias, and one where the register allocator did
the wrong thing. Fixes PR21742.
--- lib/Target/PowerPC/PPCISelLowering.cpp.orig Sun Mar 2 21:57:39 2014
+++ lib/Target/PowerPC/PPCISelLowering.cpp Sun Jul 27 04:56:45 2014
+++ lib/Target/PowerPC/PPCISelLowering.cpp Tue Dec 30 17:32:03 2014
@@ -543,6 +543,13 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine
// Altivec instructions set fields to all zeros or all ones.
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
@ -221,3 +236,16 @@ r213960
MachineInstrBuilder MIB;
@@ -8317,6 +8371,12 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const
return std::make_pair(TRI->getMatchingSuperReg(R.first,
PPC::sub_32, &PPC::G8RCRegClass),
&PPC::G8RCRegClass);
+ }
+
+ // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
+ if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
+ R.first = PPC::CR0;
+ R.second = &PPC::CRRCRegClass;
}
return R;

42
devel/llvm/patches/patch-lib_Target_PowerPC_PPCRegisterInfo_td
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@ -1,42 +0,0 @@
$OpenBSD: patch-lib_Target_PowerPC_PPCRegisterInfo_td,v 1.2 2014/12/30 22:25:47 brad Exp $
r205630
Add a full condition code register to make the "cc" clobber work
gcc inline asm supports specifying "cc" as a clobber of all condition
registers. Add just enough modeling of the full register to make this work.
Fixed PR19326.
r223328
[PowerPC] 'cc' should be an alias only to 'cr0'
We had mistakenly believed that GCC's 'cc' referred to the entire
condition-code register (cr0 through cr7) -- and implemented this in r205630 to
fix PR19326, but 'cc' is actually an alias only to 'cr0'. This is causing LLVM
to clobber too much with legacy code with inline asm using the 'cc' clobber.
Fixes PR21451.
--- lib/Target/PowerPC/PPCRegisterInfo.td.orig Sun Mar 2 21:57:39 2014
+++ lib/Target/PowerPC/PPCRegisterInfo.td Tue Dec 30 17:17:52 2014
@@ -144,6 +144,11 @@ def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>,
def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
}
+// An alias for "cr0" used by GCC.
+def CC : PPCReg<"cc">, DwarfRegAlias<CR0> {
+ let Aliases = [CR0];
+}
+
// Link register
def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
//let Aliases = [LR] in
@@ -233,3 +238,8 @@ def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VR
def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {
let CopyCost = -1;
}
+
+def CCRC : RegisterClass<"PPC", [i32], 32, (add CC)> {
+ let isAllocatable = 0;
+}
+