Update to libnettle-3.8.1.
This commit is contained in:
ajacoutot
parent
a5850db95b
commit
4ff1bb94e5
@ -1,8 +1,7 @@
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COMMENT= cryptographic library
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DISTNAME= nettle-3.8
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DISTNAME= nettle-3.8.1
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PKGNAME= lib${DISTNAME}
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REVISION= 1
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SHARED_LIBS += hogweed 3.0 # 6.3
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SHARED_LIBS += nettle 7.1 # 8.3
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@ -1,2 +1,2 @@
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SHA256 (nettle-3.8.tar.gz) = dXbGhIHBmPZEsIwWDRpIULqUSeMIBpRVtSEzGfI06OY=
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SIZE (nettle-3.8.tar.gz) = 2404258
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SHA256 (nettle-3.8.1.tar.gz) = Nk8+K3fNfc3oP9fEUhnINOVLDHXkKLb4lKI9Et1By/4=
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SIZE (nettle-3.8.1.tar.gz) = 2406251
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@ -1,148 +0,0 @@
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Fix a POSIX violation of m4 argument expansion
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https://git.lysator.liu.se/nettle/nettle/-/commit/d4c7597e4236f746434c9a1a24f6191f7ff870cd
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Index: arm64/chacha-4core.asm
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--- arm64/chacha-4core.asm.orig
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+++ arm64/chacha-4core.asm
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@@ -53,67 +53,74 @@ define(`TMP3', `v7')
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define(`ROT24', `v8')
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+C A workaround for expanding multiple digits of argument references to QR macro which is incompatible with POSIX
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+C See https://www.gnu.org/software/m4/manual/html_node/Arguments.html
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+define(`P1',
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+`ifelse($1, 0, v16, $1, 1, v17, $1, 2, v18, $1, 3, v19, $1, 4, v20, $1, 5, v21, $1, 6, v22, $1, 7, v23, $1, 8, v24, $1, 9, v25, $1, 10, v26, $1, 11, v27, $1, 12, v28, $1, 13, v29, $1, 14, v30, $1, 15, v31)')
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+define(`P2',
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+`ifelse($1, 0, v16, $1, 1, v21, $1, 2, v26, $1, 3, v31, $1, 4, v20, $1, 5, v25, $1, 6, v30, $1, 7, v19, $1, 8, v24, $1, 9, v29, $1, 10, v18, $1, 11, v23, $1, 12, v28, $1, 13, v17, $1, 14, v22, $1, 15, v27)')
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+
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C Main loop for round
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define(`QR',`
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- add $1.4s, $1.4s, $2.4s
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- add $5.4s, $5.4s, $6.4s
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- add $9.4s, $9.4s, $10.4s
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- add $13.4s, $13.4s, $14.4s
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- eor $4.16b, $4.16b, $1.16b
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- eor $8.16b, $8.16b, $5.16b
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- eor $12.16b, $12.16b, $9.16b
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- eor $16.16b, $16.16b, $13.16b
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- rev32 $4.8h, $4.8h
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- rev32 $8.8h, $8.8h
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- rev32 $12.8h, $12.8h
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- rev32 $16.8h, $16.8h
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+ add $1(0).4s, $1(0).4s, $1(1).4s
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+ add $1(4).4s, $1(4).4s, $1(5).4s
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+ add $1(8).4s, $1(8).4s, $1(9).4s
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+ add $1(12).4s, $1(12).4s, $1(13).4s
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+ eor $1(3).16b, $1(3).16b, $1(0).16b
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+ eor $1(7).16b, $1(7).16b, $1(4).16b
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+ eor $1(11).16b, $1(11).16b, $1(8).16b
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+ eor $1(15).16b, $1(15).16b, $1(12).16b
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+ rev32 $1(3).8h, $1(3).8h
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+ rev32 $1(7).8h, $1(7).8h
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+ rev32 $1(11).8h, $1(11).8h
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+ rev32 $1(15).8h, $1(15).8h
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- add $3.4s, $3.4s, $4.4s
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- add $7.4s, $7.4s, $8.4s
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- add $11.4s, $11.4s, $12.4s
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- add $15.4s, $15.4s, $16.4s
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- eor TMP0.16b, $2.16b, $3.16b
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- eor TMP1.16b, $6.16b, $7.16b
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- eor TMP2.16b, $10.16b, $11.16b
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- eor TMP3.16b, $14.16b, $15.16b
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- ushr $2.4s, TMP0.4s, #20
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- ushr $6.4s, TMP1.4s, #20
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- ushr $10.4s, TMP2.4s, #20
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- ushr $14.4s, TMP3.4s, #20
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- sli $2.4s, TMP0.4s, #12
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- sli $6.4s, TMP1.4s, #12
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- sli $10.4s, TMP2.4s, #12
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- sli $14.4s, TMP3.4s, #12
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+ add $1(2).4s, $1(2).4s, $1(3).4s
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+ add $1(6).4s, $1(6).4s, $1(7).4s
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+ add $1(10).4s, $1(10).4s, $1(11).4s
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+ add $1(14).4s, $1(14).4s, $1(15).4s
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+ eor TMP0.16b, $1(1).16b, $1(2).16b
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+ eor TMP1.16b, $1(5).16b, $1(6).16b
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+ eor TMP2.16b, $1(9).16b, $1(10).16b
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+ eor TMP3.16b, $1(13).16b, $1(14).16b
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+ ushr $1(1).4s, TMP0.4s, #20
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+ ushr $1(5).4s, TMP1.4s, #20
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+ ushr $1(9).4s, TMP2.4s, #20
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+ ushr $1(13).4s, TMP3.4s, #20
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+ sli $1(1).4s, TMP0.4s, #12
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+ sli $1(5).4s, TMP1.4s, #12
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+ sli $1(9).4s, TMP2.4s, #12
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+ sli $1(13).4s, TMP3.4s, #12
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- add $1.4s, $1.4s, $2.4s
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- add $5.4s, $5.4s, $6.4s
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- add $9.4s, $9.4s, $10.4s
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- add $13.4s, $13.4s, $14.4s
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- eor $4.16b, $4.16b, $1.16b
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- eor $8.16b, $8.16b, $5.16b
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- eor $12.16b, $12.16b, $9.16b
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- eor $16.16b, $16.16b, $13.16b
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- tbl $4.16b, {$4.16b}, ROT24.16b
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- tbl $8.16b, {$8.16b}, ROT24.16b
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- tbl $12.16b, {$12.16b}, ROT24.16b
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- tbl $16.16b, {$16.16b}, ROT24.16b
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+ add $1(0).4s, $1(0).4s, $1(1).4s
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+ add $1(4).4s, $1(4).4s, $1(5).4s
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+ add $1(8).4s, $1(8).4s, $1(9).4s
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+ add $1(12).4s, $1(12).4s, $1(13).4s
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+ eor $1(3).16b, $1(3).16b, $1(0).16b
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+ eor $1(7).16b, $1(7).16b, $1(4).16b
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+ eor $1(11).16b, $1(11).16b, $1(8).16b
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+ eor $1(15).16b, $1(15).16b, $1(12).16b
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+ tbl $1(3).16b, {$1(3).16b}, ROT24.16b
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+ tbl $1(7).16b, {$1(7).16b}, ROT24.16b
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+ tbl $1(11).16b, {$1(11).16b}, ROT24.16b
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+ tbl $1(15).16b, {$1(15).16b}, ROT24.16b
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- add $3.4s, $3.4s, $4.4s
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- add $7.4s, $7.4s, $8.4s
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- add $11.4s, $11.4s, $12.4s
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- add $15.4s, $15.4s, $16.4s
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- eor TMP0.16b, $2.16b, $3.16b
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- eor TMP1.16b, $6.16b, $7.16b
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- eor TMP2.16b, $10.16b, $11.16b
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- eor TMP3.16b, $14.16b, $15.16b
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- ushr $2.4s, TMP0.4s, #25
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- ushr $6.4s, TMP1.4s, #25
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- ushr $10.4s, TMP2.4s, #25
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- ushr $14.4s, TMP3.4s, #25
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- sli $2.4s, TMP0.4s, #7
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- sli $6.4s, TMP1.4s, #7
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- sli $10.4s, TMP2.4s, #7
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- sli $14.4s, TMP3.4s, #7
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+ add $1(2).4s, $1(2).4s, $1(3).4s
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+ add $1(6).4s, $1(6).4s, $1(7).4s
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+ add $1(10).4s, $1(10).4s, $1(11).4s
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+ add $1(14).4s, $1(14).4s, $1(15).4s
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+ eor TMP0.16b, $1(1).16b, $1(2).16b
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+ eor TMP1.16b, $1(5).16b, $1(6).16b
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+ eor TMP2.16b, $1(9).16b, $1(10).16b
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+ eor TMP3.16b, $1(13).16b, $1(14).16b
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+ ushr $1(1).4s, TMP0.4s, #25
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+ ushr $1(5).4s, TMP1.4s, #25
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+ ushr $1(9).4s, TMP2.4s, #25
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+ ushr $1(13).4s, TMP3.4s, #25
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+ sli $1(1).4s, TMP0.4s, #7
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+ sli $1(5).4s, TMP1.4s, #7
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+ sli $1(9).4s, TMP2.4s, #7
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+ sli $1(13).4s, TMP3.4s, #7
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')
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define(`TRANSPOSE',`
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@@ -174,8 +181,8 @@ C Load state and splat
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mov T3.16b, v31.16b
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.Loop:
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- QR(v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31)
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- QR(v16, v21, v26, v31, v20, v25, v30, v19, v24, v29, v18, v23, v28, v17, v22, v27)
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+ QR(`P1')
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+ QR(`P2')
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subs ROUNDS, ROUNDS, #2
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b.ne .Loop
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@ -1,39 +0,0 @@
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Enable runtime arm64 feature detection on openbsd
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https://git.lysator.liu.se/nettle/nettle/-/commit/b874bdead2903d715c6964b2e8f9ed7d2b61db12
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Index: fat-arm64.c
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--- fat-arm64.c.orig
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+++ fat-arm64.c
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@@ -46,6 +46,10 @@
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# include <asm/hwcap.h>
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# include <sys/auxv.h>
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# endif
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+#elif defined(__OpenBSD__)
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+# include <sys/sysctl.h>
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+# include <machine/cpu.h>
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+# include <machine/armreg.h>
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#endif
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#include "nettle-types.h"
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@@ -122,6 +126,21 @@ get_arm64_features (struct arm64_features *features)
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= ((hwcap & (HWCAP_ASIMD | HWCAP_SHA1)) == (HWCAP_ASIMD | HWCAP_SHA1));
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features->have_sha2
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= ((hwcap & (HWCAP_ASIMD | HWCAP_SHA2)) == (HWCAP_ASIMD | HWCAP_SHA2));
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+#elif defined(__OpenBSD__)
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+ const int isar0_mib[] = { CTL_MACHDEP, CPU_ID_AA64ISAR0 };
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+ uint64_t isar0;
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+ size_t len = sizeof(isar0);
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+
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+ if (sysctl(isar0_mib, 2, &isar0, &len, NULL, 0) < 0)
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+ return;
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+ features->have_aes
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+ = (ID_AA64ISAR0_AES(isar0) >= ID_AA64ISAR0_AES_BASE);
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+ features->have_pmull
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+ = (ID_AA64ISAR0_AES(isar0) >= ID_AA64ISAR0_AES_PMULL);
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+ features->have_sha1
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+ = (ID_AA64ISAR0_SHA1(isar0) >= ID_AA64ISAR0_SHA1_BASE);
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+ features->have_sha2
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+ = (ID_AA64ISAR0_SHA2(isar0) >= ID_AA64ISAR0_SHA2_BASE);
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#endif
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}
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}
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@ -1,132 +0,0 @@
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Fix a POSIX violation of m4 argument expansion
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https://git.lysator.liu.se/nettle/nettle/-/commit/d4c7597e4236f746434c9a1a24f6191f7ff870cd
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Index: powerpc64/p7/chacha-4core.asm
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--- powerpc64/p7/chacha-4core.asm.orig
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+++ powerpc64/p7/chacha-4core.asm
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@@ -53,59 +53,66 @@ define(`T1', `v21')
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define(`T2', `v22')
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define(`T3', `v23')
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+C A workaround for expanding multiple digits of argument references to QR macro which is incompatible with POSIX
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+C See https://www.gnu.org/software/m4/manual/html_node/Arguments.html
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+define(`P1',
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+`ifelse($1, 0, v0, $1, 1, v4, $1, 2, v8, $1, 3, v12, $1, 4, v1, $1, 5, v5, $1, 6, v9, $1, 7, v13, $1, 8, v2, $1, 9, v6, $1, 10, v10, $1, 11, v14, $1, 12, v3, $1, 13, v7, $1, 14, v11, $1, 15, v15)')
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+define(`P2',
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+`ifelse($1, 0, v0, $1, 1, v5, $1, 2, v10, $1, 3, v15, $1, 4, v1, $1, 5, v6, $1, 6, v11, $1, 7, v12, $1, 8, v2, $1, 9, v7, $1, 10, v8, $1, 11, v13, $1, 12, v3, $1, 13, v4, $1, 14, v9, $1, 15, v14)')
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+
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C Main loop for round
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define(`QR',`
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- vadduwm $1, $1, $2
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- vadduwm $5, $5, $6
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- vadduwm $9, $9, $10
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- vadduwm $13, $13, $14
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- vxor $4, $4, $1
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- vxor $8, $8, $5
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- vxor $12, $12, $9
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- vxor $16, $16, $13
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- vrlw $4, $4, ROT16
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- vrlw $8, $8, ROT16
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- vrlw $12, $12, ROT16
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- vrlw $16, $16, ROT16
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+ vadduwm $1(0), $1(0), $1(1)
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+ vadduwm $1(4), $1(4), $1(5)
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+ vadduwm $1(8), $1(8), $1(9)
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+ vadduwm $1(12), $1(12), $1(13)
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+ vxor $1(3), $1(3), $1(0)
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+ vxor $1(7), $1(7), $1(4)
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+ vxor $1(11), $1(11), $1(8)
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+ vxor $1(15), $1(15), $1(12)
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+ vrlw $1(3), $1(3), ROT16
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+ vrlw $1(7), $1(7), ROT16
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+ vrlw $1(11), $1(11), ROT16
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+ vrlw $1(15), $1(15), ROT16
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- vadduwm $3, $3, $4
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- vadduwm $7, $7, $8
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- vadduwm $11, $11, $12
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- vadduwm $15, $15, $16
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- vxor $2, $2, $3
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- vxor $6, $6, $7
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- vxor $10, $10, $11
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- vxor $14, $14, $15
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- vrlw $2, $2, ROT12
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- vrlw $6, $6, ROT12
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- vrlw $10, $10, ROT12
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- vrlw $14, $14, ROT12
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+ vadduwm $1(2), $1(2), $1(3)
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+ vadduwm $1(6), $1(6), $1(7)
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+ vadduwm $1(10), $1(10), $1(11)
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+ vadduwm $1(14), $1(14), $1(15)
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+ vxor $1(1), $1(1), $1(2)
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+ vxor $1(5), $1(5), $1(6)
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+ vxor $1(9), $1(9), $1(10)
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+ vxor $1(13), $1(13), $1(14)
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+ vrlw $1(1), $1(1), ROT12
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+ vrlw $1(5), $1(5), ROT12
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+ vrlw $1(9), $1(9), ROT12
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+ vrlw $1(13), $1(13), ROT12
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- vadduwm $1, $1, $2
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- vadduwm $5, $5, $6
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- vadduwm $9, $9, $10
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- vadduwm $13, $13, $14
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- vxor $4, $4, $1
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- vxor $8, $8, $5
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- vxor $12, $12, $9
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- vxor $16, $16, $13
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- vrlw $4, $4, ROT8
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- vrlw $8, $8, ROT8
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- vrlw $12, $12, ROT8
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- vrlw $16, $16, ROT8
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+ vadduwm $1(0), $1(0), $1(1)
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+ vadduwm $1(4), $1(4), $1(5)
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+ vadduwm $1(8), $1(8), $1(9)
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+ vadduwm $1(12), $1(12), $1(13)
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+ vxor $1(3), $1(3), $1(0)
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+ vxor $1(7), $1(7), $1(4)
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+ vxor $1(11), $1(11), $1(8)
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+ vxor $1(15), $1(15), $1(12)
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+ vrlw $1(3), $1(3), ROT8
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+ vrlw $1(7), $1(7), ROT8
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+ vrlw $1(11), $1(11), ROT8
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+ vrlw $1(15), $1(15), ROT8
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- vadduwm $3, $3, $4
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- vadduwm $7, $7, $8
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- vadduwm $11, $11, $12
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- vadduwm $15, $15, $16
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- vxor $2, $2, $3
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- vxor $6, $6, $7
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- vxor $10, $10, $11
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- vxor $14, $14, $15
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- vrlw $2, $2, ROT7
|
||||
- vrlw $6, $6, ROT7
|
||||
- vrlw $10, $10, ROT7
|
||||
- vrlw $14, $14, ROT7
|
||||
+ vadduwm $1(2), $1(2), $1(3)
|
||||
+ vadduwm $1(6), $1(6), $1(7)
|
||||
+ vadduwm $1(10), $1(10), $1(11)
|
||||
+ vadduwm $1(14), $1(14), $1(15)
|
||||
+ vxor $1(1), $1(1), $1(2)
|
||||
+ vxor $1(5), $1(5), $1(6)
|
||||
+ vxor $1(9), $1(9), $1(10)
|
||||
+ vxor $1(13), $1(13), $1(14)
|
||||
+ vrlw $1(1), $1(1), ROT7
|
||||
+ vrlw $1(5), $1(5), ROT7
|
||||
+ vrlw $1(9), $1(9), ROT7
|
||||
+ vrlw $1(13), $1(13), ROT7
|
||||
')
|
||||
|
||||
define(`TRANSPOSE',`
|
||||
@@ -185,8 +192,8 @@ C Load state and splat
|
||||
srdi ROUNDS, ROUNDS, 1
|
||||
mtctr ROUNDS
|
||||
.Loop:
|
||||
- QR(v0, v4, v8, v12, v1, v5, v9, v13, v2, v6, v10, v14, v3, v7, v11, v15)
|
||||
- QR(v0, v5, v10, v15, v1, v6, v11, v12, v2, v7, v8, v13, v3, v4, v9, v14)
|
||||
+ QR(`P1')
|
||||
+ QR(`P2')
|
||||
bdnz .Loop
|
||||
|
||||
C Add in saved original words, including counters, before
|
||||
Loading…
Reference in New Issue
Block a user