Update to llvm-5.0.1rc2.
from Brad (maintainer)
This commit is contained in:
ajacoutot
parent
591500b573
commit
1cbe63224f
@ -1,4 +1,4 @@
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# $OpenBSD: Makefile,v 1.167 2017/12/01 08:00:20 ajacoutot Exp $
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# $OpenBSD: Makefile,v 1.168 2017/12/03 10:19:37 ajacoutot Exp $
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# XXX: Remember to bump MODCLANG_VERSION in lang/clang/clang.port.mk when
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# updating this port.
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@ -13,17 +13,16 @@ MULTI_PACKAGES = -main -python
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COMMENT-main = modular, fast C/C++/ObjC compiler, static analyzer and tools
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COMMENT-python = Python bindings for Clang
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LLVM_V = 5.0.0
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LLVM_V = 5.0.1rc2
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DISTNAME = llvm-${LLVM_V}.src
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PKGNAME = llvm-${LLVM_V}
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PKGNAME-main = llvm-${LLVM_V}
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PKGNAME-python = py-llvm-${LLVM_V}
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REVISION-main = 10
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CATEGORIES = devel
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DISTFILES = llvm-${LLVM_V}.src${EXTRACT_SUFX} \
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cfe-${LLVM_V}.src${EXTRACT_SUFX} \
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lld-${LLVM_V}.src${EXTRACT_SUFX}
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MASTER_SITES = https://www.llvm.org/releases/${LLVM_V}/
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MASTER_SITES = http://prereleases.llvm.org/5.0.1/rc2/
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EXTRACT_SUFX = .tar.xz
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SHARED_LIBS = clang 6.0 \
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@ -85,7 +84,7 @@ GCC_CONFIG = x86_64-unknown-openbsd${OSREV}
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.else
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GCC_CONFIG = ${MACHINE_ARCH}-unknown-openbsd${OSREV}
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.endif
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CLANG_INCLUDE_PATH = lib/clang/${LLVM_V}/include
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CLANG_INCLUDE_PATH = lib/clang/${LLVM_V:S/rc2//}/include
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SUBST_VARS += CLANG_INCLUDE_PATH LLVM_V GCC_VER GCC_CONFIG
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post-extract:
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@ -1,6 +1,6 @@
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SHA256 (cfe-5.0.0.src.tar.xz) = AZ8jwhkt95OsdGWV6UpAOQh0n44MSEtANHbSYR3SCXA=
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SHA256 (lld-5.0.0.src.tar.xz) = OZp5IKUnjULEanv35BkYIOwjAUV6fQ1PzJpKwF3VOJc=
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SHA256 (llvm-5.0.0.src.tar.xz) = 413LrmCErc9KuzJRQSfF6r19Y7czhSzNsx4G8TcxNto=
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SIZE (cfe-5.0.0.src.tar.xz) = 11437024
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SIZE (lld-5.0.0.src.tar.xz) = 668344
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SIZE (llvm-5.0.0.src.tar.xz) = 23411980
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SHA256 (cfe-5.0.1rc2.src.tar.xz) = bQ3bGlHF9Th9Xha8iWPgDQ8H9Dw0Z7u/hac6+ihQzLk=
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SHA256 (lld-5.0.1rc2.src.tar.xz) = XeLQDzljOiO6vnLlIktGnyBErDABq2FOjz3iFSVcZAE=
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SHA256 (llvm-5.0.1rc2.src.tar.xz) = wt6EFCb6CrAZCf0B7scoaChGTLf+rOvHEFqrR+PwQqo=
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SIZE (cfe-5.0.1rc2.src.tar.xz) = 11512960
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SIZE (lld-5.0.1rc2.src.tar.xz) = 668368
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SIZE (llvm-5.0.1rc2.src.tar.xz) = 23508164
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@ -1,27 +0,0 @@
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$OpenBSD: patch-lib_CodeGen_AsmPrinter_DwarfExpression_cpp,v 1.1 2017/09/14 06:10:11 ajacoutot Exp $
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Fix a logic error in DwarfExpression::addMachineReg()
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This fixes PR34323 and thus splitting undescribable registers into
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smaller, describable sub-registers.
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Index: lib/CodeGen/AsmPrinter/DwarfExpression.cpp
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--- lib/CodeGen/AsmPrinter/DwarfExpression.cpp.orig
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+++ lib/CodeGen/AsmPrinter/DwarfExpression.cpp
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@@ -131,13 +131,12 @@ bool DwarfExpression::addMachineReg(const TargetRegist
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// Intersection between the bits we already emitted and the bits
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// covered by this subregister.
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- SmallBitVector Intersection(RegSize, false);
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- Intersection.set(Offset, Offset + Size);
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- Intersection ^= Coverage;
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+ SmallBitVector CurSubReg(RegSize, false);
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+ CurSubReg.set(Offset, Offset + Size);
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// If this sub-register has a DWARF number and we haven't covered
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// its range, emit a DWARF piece for it.
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- if (Reg >= 0 && Intersection.any()) {
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+ if (Reg >= 0 && CurSubReg.test(Coverage)) {
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// Emit a piece for any gap in the coverage.
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if (Offset > CurPos)
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DwarfRegs.push_back({-1, Offset - CurPos, nullptr});
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@ -1,47 +1,13 @@
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$OpenBSD: patch-lib_Target_AArch64_AArch64ISelLowering_cpp,v 1.5 2017/09/25 10:44:19 ajacoutot Exp $
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$OpenBSD: patch-lib_Target_AArch64_AArch64ISelLowering_cpp,v 1.6 2017/12/03 10:19:37 ajacoutot Exp $
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- [AArch64] Fix bug in store of vector 0 DAGCombine.
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Avoid using XZR/WZR directly as operands to split stores of zero
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vectors. Doing so can lead to the XZR/WZR being used by an instruction
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that doesn't allow it (e.g. add).
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Fixes bug 34674.
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- Disable the Load Stack Guard for OpenBSD on AArch64. We don't use it
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on any other platform and it causes a segfault in combination with our
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IR Stack Guard.
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Disable the Load Stack Guard for OpenBSD on AArch64. We don't use it
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on any other platform and it causes a segfault in combination with our
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IR Stack Guard.
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Index: lib/Target/AArch64/AArch64ISelLowering.cpp
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--- lib/Target/AArch64/AArch64ISelLowering.cpp.orig
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+++ lib/Target/AArch64/AArch64ISelLowering.cpp
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@@ -9347,11 +9347,20 @@ static SDValue replaceZeroVectorStore(SelectionDAG &DA
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return SDValue();
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}
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- // Use WZR/XZR here to prevent DAGCombiner::MergeConsecutiveStores from
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- // undoing this transformation.
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- SDValue SplatVal = VT.getVectorElementType().getSizeInBits() == 32
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- ? DAG.getRegister(AArch64::WZR, MVT::i32)
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- : DAG.getRegister(AArch64::XZR, MVT::i64);
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+ // Use a CopyFromReg WZR/XZR here to prevent
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+ // DAGCombiner::MergeConsecutiveStores from undoing this transformation.
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+ SDLoc DL(&St);
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+ unsigned ZeroReg;
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+ EVT ZeroVT;
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+ if (VT.getVectorElementType().getSizeInBits() == 32) {
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+ ZeroReg = AArch64::WZR;
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+ ZeroVT = MVT::i32;
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+ } else {
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+ ZeroReg = AArch64::XZR;
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+ ZeroVT = MVT::i64;
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+ }
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+ SDValue SplatVal =
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+ DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT);
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return splitStoreSplat(DAG, St, SplatVal, NumVecElts);
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}
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@@ -10568,7 +10577,8 @@ void AArch64TargetLowering::ReplaceNodeResults(
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@@ -10577,7 +10577,8 @@ void AArch64TargetLowering::ReplaceNodeResults(
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}
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bool AArch64TargetLowering::useLoadStackGuardNode() const {
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@ -1,41 +0,0 @@
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$OpenBSD: patch-lib_Target_X86_X86ISelLowering_cpp,v 1.4 2017/09/16 07:01:33 ajacoutot Exp $
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[X86] Don't create i64 constants on 32-bit targets when lowering v64i1 constant build
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vectors
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When handling a v64i1 build vector of constants on 32-bit targets we were creating an
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illegal i64 constant that we then bitcasted back to v64i1. We need to instead create
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two 32-bit constants, bitcast them to v32i1 and concat the result. We should also
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take care to handle the halves being all zeros/ones after the split.
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This patch splits the build vector and then recursively lowers the two pieces. This
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allows us to handle the all ones and all zeros cases with minimal effort. Ideally
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we'd just do the split and concat, and let lowering get called again on the new
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nodes, but getNode has special handling for CONCAT_VECTORS that reassembles the
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pieces back into a single BUILD_VECTOR. Hopefully the two temporary BUILD_VECTORS we
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had to create to do this that don't get returned don't cause any issues.
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Fixes PR34605.
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Index: lib/Target/X86/X86ISelLowering.cpp
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--- lib/Target/X86/X86ISelLowering.cpp.orig
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+++ lib/Target/X86/X86ISelLowering.cpp
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@@ -7026,6 +7026,18 @@ X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, S
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return DAG.getTargetConstant(1, dl, VT);
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if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
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+ if (VT == MVT::v64i1 && !Subtarget.is64Bit()) {
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+ // Split the pieces.
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+ SDValue Lower =
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+ DAG.getBuildVector(MVT::v32i1, dl, Op.getNode()->ops().slice(0, 32));
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+ SDValue Upper =
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+ DAG.getBuildVector(MVT::v32i1, dl, Op.getNode()->ops().slice(32, 32));
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+ // We have to manually lower both halves so getNode doesn't try to
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+ // reassemble the build_vector.
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+ Lower = LowerBUILD_VECTORvXi1(Lower, DAG);
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+ Upper = LowerBUILD_VECTORvXi1(Upper, DAG);
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+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lower, Upper);
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+ }
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SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
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if (Imm.getValueSizeInBits() == VT.getSizeInBits())
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return DAG.getBitcast(VT, Imm);
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@ -1,21 +0,0 @@
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$OpenBSD: patch-tools_clang_include_clang_Basic_BuiltinsX86_def,v 1.1 2017/10/07 12:08:33 ajacoutot Exp $
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[X86] Disable _mm512_maskz_set1_epi64 intrinsic on 32-bit targets to prevent a
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backend isel failure.
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The __builtin_ia32_pbroadcastq512_mem_mask we were previously trying to use in
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32-bit mode is not implemented in the x86 backend and causes isel to fail in
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release builds. In debug builds it fails even earlier during legalization with
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an llvm_unreachable.
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Index: tools/clang/include/clang/Basic/BuiltinsX86.def
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--- tools/clang/include/clang/Basic/BuiltinsX86.def.orig
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+++ tools/clang/include/clang/Basic/BuiltinsX86.def
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@@ -976,7 +976,6 @@ TARGET_BUILTIN(__builtin_ia32_pmuludq512, "V8LLiV16iV1
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TARGET_BUILTIN(__builtin_ia32_ptestmd512, "UsV16iV16iUs", "", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_ptestmq512, "UcV8LLiV8LLiUc", "", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_pbroadcastd512_gpr_mask, "V16iiV16iUs", "", "avx512f")
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-TARGET_BUILTIN(__builtin_ia32_pbroadcastq512_mem_mask, "V8LLiLLiV8LLiUc", "", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_loaddqusi512_mask, "V16iiC*V16iUs", "", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_loaddqudi512_mask, "V8LLiLLiC*V8LLiUc", "", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_loadups512_mask, "V16ffC*V16fUs", "", "avx512f")
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@ -1,4 +1,4 @@
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$OpenBSD: patch-tools_clang_lib_Driver_ToolChains_Clang_cpp,v 1.2 2017/09/08 05:58:19 ajacoutot Exp $
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$OpenBSD: patch-tools_clang_lib_Driver_ToolChains_Clang_cpp,v 1.3 2017/12/03 10:19:37 ajacoutot Exp $
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- Make LLVM create strict aligned code for OpenBSD/arm64.
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- Disable -fstrict-aliasing per default on OpenBSD.
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@ -21,7 +21,7 @@ Index: tools/clang/lib/Driver/ToolChains/Clang.cpp
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break;
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case llvm::Triple::x86:
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case llvm::Triple::x86_64:
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@@ -2304,9 +2304,12 @@ void Clang::ConstructJob(Compilation &C, const JobActi
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@@ -2308,9 +2308,12 @@ void Clang::ConstructJob(Compilation &C, const JobActi
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OFastEnabled ? options::OPT_Ofast : options::OPT_fstrict_aliasing;
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// We turn strict aliasing off by default if we're in CL mode, since MSVC
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// doesn't do any TBAA.
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@ -36,7 +36,7 @@ Index: tools/clang/lib/Driver/ToolChains/Clang.cpp
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CmdArgs.push_back("-relaxed-aliasing");
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if (!Args.hasFlag(options::OPT_fstruct_path_tbaa,
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options::OPT_fno_struct_path_tbaa))
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@@ -3292,7 +3295,8 @@ void Clang::ConstructJob(Compilation &C, const JobActi
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@@ -3296,7 +3299,8 @@ void Clang::ConstructJob(Compilation &C, const JobActi
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options::OPT_fno_strict_overflow)) {
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if (A->getOption().matches(options::OPT_fno_strict_overflow))
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CmdArgs.push_back("-fwrapv");
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@ -46,7 +46,7 @@ Index: tools/clang/lib/Driver/ToolChains/Clang.cpp
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if (Arg *A = Args.getLastArg(options::OPT_freroll_loops,
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options::OPT_fno_reroll_loops))
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@@ -4228,6 +4232,18 @@ void Clang::ConstructJob(Compilation &C, const JobActi
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@@ -4232,6 +4236,18 @@ void Clang::ConstructJob(Compilation &C, const JobActi
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CmdArgs.push_back("-fno-builtin-strcpy");
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}
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#endif
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@ -1,37 +0,0 @@
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$OpenBSD: patch-tools_clang_lib_Headers_avx512fintrin_h,v 1.1 2017/10/07 12:08:33 ajacoutot Exp $
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[X86] Disable _mm512_maskz_set1_epi64 intrinsic on 32-bit targets to prevent a
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backend isel failure.
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The __builtin_ia32_pbroadcastq512_mem_mask we were previously trying to use in
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32-bit mode is not implemented in the x86 backend and causes isel to fail in
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release builds. In debug builds it fails even earlier during legalization with
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an llvm_unreachable.
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Index: tools/clang/lib/Headers/avx512fintrin.h
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--- tools/clang/lib/Headers/avx512fintrin.h.orig
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+++ tools/clang/lib/Headers/avx512fintrin.h
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@@ -267,21 +267,16 @@ _mm512_maskz_set1_epi32(__mmask16 __M, int __A)
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__M);
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}
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+#ifdef __x86_64__
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static __inline __m512i __DEFAULT_FN_ATTRS
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_mm512_maskz_set1_epi64(__mmask8 __M, long long __A)
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{
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-#ifdef __x86_64__
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return (__m512i) __builtin_ia32_pbroadcastq512_gpr_mask (__A,
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(__v8di)
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_mm512_setzero_si512 (),
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__M);
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-#else
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- return (__m512i) __builtin_ia32_pbroadcastq512_mem_mask (__A,
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- (__v8di)
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- _mm512_setzero_si512 (),
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- __M);
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-#endif
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}
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+#endif
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static __inline __m512 __DEFAULT_FN_ATTRS
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_mm512_setzero_ps(void)
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@ -1,56 +0,0 @@
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$OpenBSD: patch-tools_lld_ELF_SyntheticSections_cpp,v 1.4 2017/10/08 07:40:18 ajacoutot Exp $
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- [ELF] - Fix segfault when processing .eh_frame.
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Its a PR34648 which was a segfault that happened because
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we stored pointers to elements in DenseMap.
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When DenseMap grows such pointers are invalidated.
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Solution implemented is to keep elements by pointer
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and not by value.
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- [LLD] Fix padding of .eh_frame when in executable segment
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The default padding for an executable segment is the target trap
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instruction which for x86_64 is 0xCC. However, the .eh_frame section
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requires the padding to be zero. The code that writes the .eh_frame
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section assumes that its segment is zero initialized and does not
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explicitly write the zero padding. This does not work when the .eh_frame
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section is in the executable segment (for example when using
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-no-rosegment).
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This patch changes the .eh_frame writing code to explicitly write the
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zero padding.
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Index: tools/lld/ELF/SyntheticSections.cpp
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--- tools/lld/ELF/SyntheticSections.cpp.orig
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+++ tools/lld/ELF/SyntheticSections.cpp
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@@ -427,10 +427,11 @@ CieRecord *EhFrameSection<ELFT>::addCie(EhSectionPiece
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&Sec->template getFile<ELFT>()->getRelocTargetSym(Rels[FirstRelI]);
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// Search for an existing CIE by CIE contents/relocation target pair.
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- CieRecord *Cie = &CieMap[{Piece.data(), Personality}];
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+ CieRecord *&Cie = CieMap[{Piece.data(), Personality}];
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// If not found, create a new one.
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- if (Cie->Piece == nullptr) {
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+ if (!Cie) {
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+ Cie = make<CieRecord>();
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Cie->Piece = &Piece;
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Cies.push_back(Cie);
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}
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@@ -522,9 +523,14 @@ template <class ELFT>
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static void writeCieFde(uint8_t *Buf, ArrayRef<uint8_t> D) {
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memcpy(Buf, D.data(), D.size());
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+ size_t Aligned = alignTo(D.size(), sizeof(typename ELFT::uint));
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+
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+ // Zero-clear trailing padding if it exists.
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+ memset(Buf + D.size(), 0, Aligned - D.size());
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+
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// Fix the size field. -4 since size does not include the size field itself.
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const endianness E = ELFT::TargetEndianness;
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- write32<E>(Buf, alignTo(D.size(), sizeof(typename ELFT::uint)) - 4);
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+ write32<E>(Buf, Aligned - 4);
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}
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template <class ELFT> void EhFrameSection<ELFT>::finalizeContents() {
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@ -1,23 +0,0 @@
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$OpenBSD: patch-tools_lld_ELF_SyntheticSections_h,v 1.1 2017/10/08 07:40:18 ajacoutot Exp $
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[ELF] - Fix segfault when processing .eh_frame.
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|
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Its a PR34648 which was a segfault that happened because
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we stored pointers to elements in DenseMap.
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When DenseMap grows such pointers are invalidated.
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Solution implemented is to keep elements by pointer
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and not by value.
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Index: tools/lld/ELF/SyntheticSections.h
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--- tools/lld/ELF/SyntheticSections.h.orig
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+++ tools/lld/ELF/SyntheticSections.h
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@@ -103,7 +103,8 @@ template <class ELFT> class EhFrameSection final : pub
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std::vector<CieRecord *> Cies;
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// CIE records are uniquified by their contents and personality functions.
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- llvm::DenseMap<std::pair<ArrayRef<uint8_t>, SymbolBody *>, CieRecord> CieMap;
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+ llvm::DenseMap<std::pair<ArrayRef<uint8_t>, SymbolBody *>, CieRecord *>
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+ CieMap;
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};
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||||
|
||||
class GotSection : public SyntheticSection {
|
||||
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Reference in New Issue
Block a user