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openbsd-ports/cad/tkgate/Makefile

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first tag: update-desktop-database
2018-06-27 21:03:34 +00:00
# $OpenBSD: Makefile,v 1.4 2018/06/27 21:03:38 espie Exp $
Import tkgate after new upstream fixed all the bugs. request, fixes and ok from jasper@ TkGate is a graphical editor and event-driven simulator for digital circuits with a tcl/tk-based interface. Supported circuit elements include basic gates (AND, OR, etc.), tri-state gates, adders, multipliers, registers, memories and mos transistors. Hierarchical design is also supported with support for user defined modules. Save files are based on the Verilog netlist format.
2015-04-07 14:00:07 +00:00
COMMENT = Tcl/Tk based digital circuit editor and simulator
DISTNAME = tkgate-2.0-rc3
PKGNAME = tkgate-2.0rc3
first tag: update-desktop-database
2018-06-27 21:03:34 +00:00
REVISION = 1
Import tkgate after new upstream fixed all the bugs. request, fixes and ok from jasper@ TkGate is a graphical editor and event-driven simulator for digital circuits with a tcl/tk-based interface. Supported circuit elements include basic gates (AND, OR, etc.), tri-state gates, adders, multipliers, registers, memories and mos transistors. Hierarchical design is also supported with support for user defined modules. Save files are based on the Verilog netlist format.
2015-04-07 14:00:07 +00:00
CATEGORIES = cad x11
MAINTAINER = Kirill Bychkov <kirby@openbsd.org>
MASTER_SITES = https://bitbucket.org/starling13/tkgate/downloads/
# GPLv2+
PERMIT_PACKAGE_CDROM = Yes
replace libiconv module
2016-09-13 11:44:06 +00:00
WANTLIB += ICE SM X11 c iconv m pthread ${MODTK_WANTLIB}
Import tkgate after new upstream fixed all the bugs. request, fixes and ok from jasper@ TkGate is a graphical editor and event-driven simulator for digital circuits with a tcl/tk-based interface. Supported circuit elements include basic gates (AND, OR, etc.), tri-state gates, adders, multipliers, registers, memories and mos transistors. Hierarchical design is also supported with support for user defined modules. Save files are based on the Verilog netlist format.
2015-04-07 14:00:07 +00:00
replace libiconv module
2016-09-13 11:44:06 +00:00
MODULES = x11/tk
Import tkgate after new upstream fixed all the bugs. request, fixes and ok from jasper@ TkGate is a graphical editor and event-driven simulator for digital circuits with a tcl/tk-based interface. Supported circuit elements include basic gates (AND, OR, etc.), tri-state gates, adders, multipliers, registers, memories and mos transistors. Hierarchical design is also supported with support for user defined modules. Save files are based on the Verilog netlist format.
2015-04-07 14:00:07 +00:00
replace libiconv module
2016-09-13 11:44:06 +00:00
LIB_DEPENDS = converters/libiconv
Import tkgate after new upstream fixed all the bugs. request, fixes and ok from jasper@ TkGate is a graphical editor and event-driven simulator for digital circuits with a tcl/tk-based interface. Supported circuit elements include basic gates (AND, OR, etc.), tri-state gates, adders, multipliers, registers, memories and mos transistors. Hierarchical design is also supported with support for user defined modules. Save files are based on the Verilog netlist format.
2015-04-07 14:00:07 +00:00
BUILD_DEPENDS = ${MODTK_BUILD_DEPENDS}
RUN_DEPENDS = ${MODTK_RUN_DEPENDS} \
devel/desktop-file-utils
SEPARATE_BUILD = Yes
CONFIGURE_STYLE = gnu
CONFIGURE_ENV += TKGATE_LIBDIRS="${MODTCL_LIBDIR} ${MODTK_LIBDIR} \
${LOCALBASE}/lib ${X11BASE}/lib" \
TKGATE_INCDIRS="${MODTCL_INCDIR} ${MODTK_INCDIR} \
${LOCALBASE}/include ${X11BASE}/include" \
TKGATE_TCLTK_VERSIONS=${MODTK_VERSION}
post-extract:
rm ${WRKSRC}/src/gmac/luthor.c
rm ${WRKSRC}/src/verga/luthor.c
rm ${WRKSRC}/src/verga/vgrammar.c
rm ${WRKSRC}/src/verga/vgrammar.h
rm ${WRKSRC}/src/tkgate/luthor.c
rm ${WRKSRC}/src/tkgate/vgrammar.c
rm ${WRKSRC}/src/tkgate/vgrammar.h
pre-configure:
${SUBST_CMD} ${WRKSRC}/scripts/parms.tcl ${WRKSRC}/src/tkgate/verilog_out.c
${MODTCL_WISH_ADJ} ${WRKSRC}/scripts/tree.tcl
post-install:
rm ${PREFIX}/share/tkgate/scripts/parms.tcl.*
.include <bsd.port.mk>
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