30a00f2227
hide actual commands executed and only show short summary line (like "CC foo.c"). CMake and ninja enable this by default, some autotools using ports do as well. This is unacceptable because we need complete build logs at any time, so we now switch to verbose build logs unconditionally. Note that this change deliberately affects ALL builds and not only package builds on cluster, because we need to be sure that user experiencing failure can always provide informative build log regardless of settings and without rerunning the build. Change summary: - Always do verbose builds for cmake, ninja and GNU configure (the latter includes check if --disable-silent-rules is actually supported by the configure script; there are isolated cases when it's not true) - Remove CMAKE_VERBOSE, NINJA_VERBOSE and CONFIGURE_ARGS=--disable-silent-rules from all ports which set them for this is no longer needed - Revert hacks for --disable-silent-rules support priorly committed to biology/ncbi-blast+ and net-p2p/mldonkey - no longer needed as well Submitted by: amdmi3 Reviewed by: mat Exp-run by: antoine Approved by: portmgr (mat, antoine) Differential Revision: D7534 |
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| .. | ||
| admesh | ||
| adms | ||
| alliance | ||
| astk-client | ||
| astk-serveur | ||
| atlc | ||
| basicdsp | ||
| brickutils | ||
| brlcad | ||
| calculix | ||
| cascade | ||
| chipvault | ||
| cider | ||
| cura-engine | ||
| dinotrace | ||
| dxf2fig | ||
| electric | ||
| electric-ng | ||
| elmerfem | ||
| feappv | ||
| fidocadj | ||
| freecad | ||
| freehdl | ||
| fritzing | ||
| gdsreader | ||
| gdt | ||
| geda | ||
| gerbv | ||
| ghdl | ||
| gmsh | ||
| gmsh-occ | ||
| gnucap | ||
| gplcver | ||
| gspiceui | ||
| gtkwave | ||
| impact | ||
| irsim | ||
| iverilog | ||
| jspice3 | ||
| kicad | ||
| kicad-devel | ||
| klayout | ||
| layouteditor | ||
| ldraw | ||
| leocad | ||
| librecad | ||
| linux-eagle5 | ||
| linuxcnc-devel | ||
| logisim | ||
| magic | ||
| meshdev | ||
| meshlab | ||
| NASTRAN-95 | ||
| netgen | ||
| ngspice_rework | ||
| opencascade | ||
| openscad | ||
| openvsp | ||
| p5-GDS2 | ||
| p5-Verilog-Perl | ||
| pcb | ||
| pdnmesh | ||
| py-gdspy | ||
| py-lcapy | ||
| py-pycam | ||
| pythoncad | ||
| qcad | ||
| qelectrotech | ||
| qfsm | ||
| qmls | ||
| qucs | ||
| repsnapper | ||
| rubygem-gdsii | ||
| sceptre | ||
| scotch | ||
| spice | ||
| stepcode | ||
| sweethome3d | ||
| tkgate | ||
| tochnog | ||
| transcalc | ||
| varkon | ||
| verilog-mode.el | ||
| xcircuit | ||
| z88 | ||
| Makefile | ||