freebsd-ports/cad/Makefile
Ying-Chieh Liao 74f0872c5b add chipvault 200211
A project organizer for VHDL and Verilog RTL hardware designs
2003-01-29 03:45:13 +00:00

47 lines
933 B
Makefile

# $FreeBSD$
#
SUBDIR += atlc
SUBDIR += cascade
SUBDIR += chipmunk
SUBDIR += chipvault
SUBDIR += cider
SUBDIR += electric
SUBDIR += felt
SUBDIR += geda
SUBDIR += geda-symbols
SUBDIR += geda-symcheck
SUBDIR += geda-utils
SUBDIR += gerbv
SUBDIR += gnetlist
SUBDIR += gnucap
SUBDIR += gschem
SUBDIR += gtkwave
SUBDIR += gwave
SUBDIR += irsim
SUBDIR += iverilog
SUBDIR += kaskade
SUBDIR += leocad
SUBDIR += libgeda
SUBDIR += linux-eagle
SUBDIR += magic
SUBDIR += mars
SUBDIR += ngspice_rework
SUBDIR += oregano
SUBDIR += pcb
SUBDIR += pdnmesh
SUBDIR += pisces
SUBDIR += qcad
SUBDIR += qfsm
SUBDIR += qmls
SUBDIR += sceptre
SUBDIR += sis
SUBDIR += slffea
SUBDIR += spice
SUBDIR += tkgate
SUBDIR += transcalc
SUBDIR += vipec
SUBDIR += xcircuit
.include <bsd.port.subdir.mk>