freebsd-ports/cad/iverilog/Makefile
Marcus Alves Grando 371f431d81 Update to 0.8.1
Add second MASTER_SITES
Add SHA256

PR:		88749
Submitted by:	Joachim Strombergson <watchman@ludd.ltu.se> (maintainer)
2005-11-09 21:36:06 +00:00

27 lines
623 B
Makefile

# ex:ts=8
# New ports collection makefile for: iverilog
# Date created: Feb 13, 2001
# Whom: Ying-Chieh Liao <ijliao@FreeBSD.org>
#
# $FreeBSD$
#
PORTNAME= iverilog
PORTVERSION= 0.8.1
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/ \
ftp://ftp.geda.seul.org/pub/geda/dist/
DISTNAME= verilog-${PORTVERSION}
MAINTAINER= watchman@ludd.ltu.se
COMMENT= A Verilog simulation and synthesis tool
USE_BISON= yes
USE_GMAKE= yes
GNU_CONFIGURE= yes
CONFIGURE_TARGET= --build=${MACHINE_ARCH}-portbld-freebsd${OSREL}
MAN1= iverilog-vpi.1 iverilog.1 vvp.1 iverilog-fpga.1
.include <bsd.port.mk>