fb16dfecae
Commit b7f05445c0 has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner)
4 lines
179 B
Plaintext
4 lines
179 B
Plaintext
Yosys is a framework for Verilog RTL synthesis. It currently has
|
|
extensive Verilog-2005 support and provides a basic set of synthesis
|
|
algorithms for various application domains.
|