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- Update to 20181005 snapshot

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Sponsored by:	The FreeBSD Foundation
This commit is contained in:
Li-Wen Hsu 2018-10-05 11:07:12 +00:00
parent 76de673520
commit db3dfea2ca
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=481273
6 changed files with 21 additions and 16 deletions
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10
emulators/riscv-isa-sim/Makefile
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@ -2,7 +2,7 @@
PORTNAME= riscv-isa-sim
DISTVERSION= git
PORTREVISION= 20180104
PORTREVISION= 20181005
CATEGORIES= emulators
MAINTAINER= lwhsu@FreeBSD.org
@ -10,15 +10,15 @@ COMMENT= Spike, a RISC-V ISA Simulator
LICENSE= BSD3CLAUSE
LIB_DEPENDS= libfesvr.so:emulators/riscv-fesvr
ONLY_FOR_ARCHS= amd64
GH_ACCOUNT= freebsd-riscv
GH_TAGNAME= acf9589
LIB_DEPENDS= libfesvr.so:emulators/riscv-fesvr
USES= compiler:c++11-lang gmake shebangfix
GH_ACCOUNT= freebsd-riscv
GH_TAGNAME= aae60e0
HAS_CONFIGURE= yes
SHEBANG_FILES= scripts/vcs-version.sh
USE_GITHUB= yes

6
emulators/riscv-isa-sim/distinfo
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@ -1,3 +1,3 @@
TIMESTAMP = 1515149913
SHA256 (freebsd-riscv-riscv-isa-sim-git-acf9589_GH0.tar.gz) = 163689110e1742271b02984f378974418d23d69e7c1943b75ebca0761769693b
SIZE (freebsd-riscv-riscv-isa-sim-git-acf9589_GH0.tar.gz) = 227934
TIMESTAMP = 1538736497
SHA256 (freebsd-riscv-riscv-isa-sim-git-aae60e0_GH0.tar.gz) = 423005144e71b272fad7f13b57af7de561a178af096a71d304e0a3c590520195
SIZE (freebsd-riscv-riscv-isa-sim-git-aae60e0_GH0.tar.gz) = 232817

6
emulators/riscv-isa-sim/files/patch-Makefile.in
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@ -1,6 +1,6 @@
--- Makefile.in.orig 2017-08-08 20:00:25.889361000 +0100
+++ Makefile.in 2017-08-08 20:06:41.633896000 +0100
@@ -187,13 +187,13 @@
--- Makefile.in.orig 2018-10-05 10:52:51 UTC
+++ Makefile.in
@@ -187,13 +187,13 @@ _$(1).cc :
# Build the object files for this subproject

2
emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc
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@ -1,4 +1,4 @@
--- riscv/insn_template.cc.orig 2016-08-01 15:40:47 UTC
--- riscv/insn_template.cc.orig 2018-10-05 10:52:33 UTC
+++ riscv/insn_template.cc
@@ -1,6 +1,6 @@
// See LICENSE for license details.

9
emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in
View File

@ -1,6 +1,6 @@
--- riscv/riscv.mk.in.orig 2017-07-11 13:58:22.000000000 +0100
+++ riscv/riscv.mk.in 2017-08-08 20:08:06.247906000 +0100
@@ -21,14 +21,14 @@
--- riscv/riscv.mk.in.orig 2018-10-05 10:52:11 UTC
+++ riscv/riscv.mk.in
@@ -23,7 +23,7 @@ riscv_hdrs = \
tracer.h \
extension.h \
rocc.h \
@ -8,7 +8,8 @@
+ insn_template.hpp \
mulhi.h \
debug_module.h \
remote_bitbang.h \
debug_rom_defines.h \
@@ -31,7 +31,7 @@ riscv_hdrs = \
jtag_dtm.h \
riscv_precompiled_hdrs = \

4
emulators/riscv-isa-sim/pkg-plist
View File

@ -6,9 +6,11 @@ include/spike/cachesim.h
include/spike/common.h
include/spike/config.h
include/spike/debug_module.h
include/spike/debug_rom_defines.h
include/spike/decode.h
include/spike/devices.h
include/spike/disasm.h
include/spike/dts.h
include/spike/encoding.h
include/spike/extension.h
include/spike/icache.h
@ -19,12 +21,14 @@ include/spike/jtag_dtm.h
include/spike/memtracer.h
include/spike/mmu.h
include/spike/mulhi.h
include/spike/platform.h
include/spike/primitiveTypes.h
include/spike/primitives.h
include/spike/processor.h
include/spike/remote_bitbang.h
include/spike/rocc.h
include/spike/sim.h
include/spike/simif.h
include/spike/softfloat.h
include/spike/softfloat_types.h
include/spike/specialize.h