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cad/silice: New port: Language that simplifies prototyping and writing algorithms for FPGAs

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This commit is contained in:
Yuri Victorovich 2023-01-08 01:40:18 -08:00
parent f8bbe9d10a
commit d726e22a21
5 changed files with 160 additions and 0 deletions
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1
cad/Makefile
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@ -125,6 +125,7 @@
SUBDIR += repsnapper
SUBDIR += rubygem-gdsii
SUBDIR += scotch
SUBDIR += silice
SUBDIR += solvespace
SUBDIR += sp2sp
SUBDIR += spice

39
cad/silice/Makefile Normal file
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@ -0,0 +1,39 @@
PORTNAME= silice
DISTVERSION= g20221229
CATEGORIES= cad
MAINTAINER= yuri@FreeBSD.org
COMMENT= Language that simplifies prototyping and writing algorithms for FPGAs
WWW= https://github.com/sylefeb/Silice
LICENSE= GPLv3
LICENSE_FILE= ${WRKSRC}/LICENSE_GPLv3
BUILD_DEPENDS= bash:shells/bash
RUN_DEPENDS= ${PYTHON_PKGNAMEPREFIX}edalize>0:cad/py-edalize@${PY_FLAVOR} # examples also require xtclsh from Xilinx
USES= cmake:noninja python shebangfix
USE_JAVA= yes
JAVA_VERSION= 17
USE_GITHUB= yes
GH_ACCOUNT= sylefeb
GH_PROJECT= Silice
GH_TAGNAME= 6a2beda
GH_TUPLE= sylefeb:LibSL-small:b1942d5:LibSL_small/src/libs/LibSL-small \
sylefeb:tinygpus:e6429ac:tinygpus/projects/tinygpus \
ultraembedded:fat_io_lib:0ef5c2b:fat_io_lib/learn-silice/classroom/soc_wave_player/firmware/fat_io_lib
SHEBANG_GLOB= *.sh *.py
do-install:
${INSTALL_PROGRAM} ${BUILD_WRKSRC}/${PORTNAME} ${STAGEDIR}${PREFIX}/bin
${INSTALL_SCRIPT} ${WRKSRC}/bin/silice-make.py ${STAGEDIR}${PREFIX}/bin
${REINPLACE_CMD} \
-i '' \
-e 's|frameworks_dir = os.path.realpath(os.path.join(make_dir,"../frameworks/"))|frameworks_dir = "${DATADIR}/frameworks"|' \
${STAGEDIR}${PREFIX}/bin/silice-make.py
cd ${WRKSRC} && ${COPYTREE_SHARE} frameworks ${STAGEDIR}${DATADIR}
.include <bsd.port.mk>

9
cad/silice/distinfo Normal file
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@ -0,0 +1,9 @@
TIMESTAMP = 1673143292
SHA256 (sylefeb-Silice-g20221229-6a2beda_GH0.tar.gz) = 5577d91ccac7e26204a034d262faa6107bbf06fdefe7107b3a5670364384f59c
SIZE (sylefeb-Silice-g20221229-6a2beda_GH0.tar.gz) = 42949179
SHA256 (sylefeb-LibSL-small-b1942d5_GH0.tar.gz) = dbea9ba30c4e40e3e9e6da840e90eb9e0a91b0355dc3ae0e72602d70d718d8fd
SIZE (sylefeb-LibSL-small-b1942d5_GH0.tar.gz) = 72760
SHA256 (sylefeb-tinygpus-e6429ac_GH0.tar.gz) = 5e1cdfae1b81402acbeb118f350537599fd74cb8e2bc486ea6cb753ffe8f0d05
SIZE (sylefeb-tinygpus-e6429ac_GH0.tar.gz) = 1435993
SHA256 (ultraembedded-fat_io_lib-0ef5c2b_GH0.tar.gz) = a88b5a3b0707931e7b2689d8f886b7dac53c9c4262aa9b3938d91a065c114079
SIZE (ultraembedded-fat_io_lib-0ef5c2b_GH0.tar.gz) = 52464

3
cad/silice/pkg-descr Normal file
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@ -0,0 +1,3 @@
Yosys is a framework for Verilog RTL synthesis. It currently has
extensive Verilog-2005 support and provides a basic set of synthesis
algorithms for various application domains.

108
cad/silice/pkg-plist Normal file
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@ -0,0 +1,108 @@
bin/silice
bin/silice-make.py
%%DATADIR%%/frameworks/boards/README.md
%%DATADIR%%/frameworks/boards/bare/bare.sh
%%DATADIR%%/frameworks/boards/bare/bare.v
%%DATADIR%%/frameworks/boards/bare/board.json
%%DATADIR%%/frameworks/boards/boards.json
%%DATADIR%%/frameworks/boards/crosslink_nx_evn/board.json
%%DATADIR%%/frameworks/boards/crosslink_nx_evn/crosslink_nx_evn.pdc
%%DATADIR%%/frameworks/boards/crosslink_nx_evn/crosslink_nx_evn.sh
%%DATADIR%%/frameworks/boards/crosslink_nx_evn/crosslink_nx_evn.v
%%DATADIR%%/frameworks/boards/de10nano/board.json
%%DATADIR%%/frameworks/boards/de10nano/build.sdc
%%DATADIR%%/frameworks/boards/de10nano/de10nano.v
%%DATADIR%%/frameworks/boards/de10nano/pins.tcl
%%DATADIR%%/frameworks/boards/ecpix5/board.json
%%DATADIR%%/frameworks/boards/ecpix5/ecpix5.lpf
%%DATADIR%%/frameworks/boards/ecpix5/ecpix5.v
%%DATADIR%%/frameworks/boards/fomu/board.json
%%DATADIR%%/frameworks/boards/fomu/fomu-hacker.pcf
%%DATADIR%%/frameworks/boards/fomu/fomu-hacker.sh
%%DATADIR%%/frameworks/boards/fomu/fomu-pvt1.pcf
%%DATADIR%%/frameworks/boards/fomu/fomu-pvt1.sh
%%DATADIR%%/frameworks/boards/fomu/fomu.v
%%DATADIR%%/frameworks/boards/formal/board.json
%%DATADIR%%/frameworks/boards/formal/formal.sh
%%DATADIR%%/frameworks/boards/formal/formal.v
%%DATADIR%%/frameworks/boards/icarus/board.json
%%DATADIR%%/frameworks/boards/icarus/icarus.sh
%%DATADIR%%/frameworks/boards/icarus/icarus.v
%%DATADIR%%/frameworks/boards/icebitsy/board.json
%%DATADIR%%/frameworks/boards/icebitsy/icebitsy.pcf
%%DATADIR%%/frameworks/boards/icebitsy/icebitsy.v
%%DATADIR%%/frameworks/boards/icebreaker/board.json
%%DATADIR%%/frameworks/boards/icebreaker/icebreaker.pcf
%%DATADIR%%/frameworks/boards/icebreaker/icebreaker.sh
%%DATADIR%%/frameworks/boards/icebreaker/icebreaker.v
%%DATADIR%%/frameworks/boards/icestick/board.json
%%DATADIR%%/frameworks/boards/icestick/icestick.pcf
%%DATADIR%%/frameworks/boards/icestick/icestick.sh
%%DATADIR%%/frameworks/boards/icestick/icestick.v
%%DATADIR%%/frameworks/boards/littlebee/board.json
%%DATADIR%%/frameworks/boards/littlebee/littlebee.cst
%%DATADIR%%/frameworks/boards/littlebee/littlebee.sh
%%DATADIR%%/frameworks/boards/littlebee/littlebee.v
%%DATADIR%%/frameworks/boards/mch2022/board.json
%%DATADIR%%/frameworks/boards/mch2022/mch2022.pcf
%%DATADIR%%/frameworks/boards/mch2022/mch2022.sh
%%DATADIR%%/frameworks/boards/mch2022/mch2022.v
%%DATADIR%%/frameworks/boards/minimal/board.json
%%DATADIR%%/frameworks/boards/minimal/minimal.sh
%%DATADIR%%/frameworks/boards/minimal/minimal.v
%%DATADIR%%/frameworks/boards/mojov3/board.json
%%DATADIR%%/frameworks/boards/mojov3/mojov3.ucf
%%DATADIR%%/frameworks/boards/mojov3/mojov3.v
%%DATADIR%%/frameworks/boards/orangecrab/board.json
%%DATADIR%%/frameworks/boards/orangecrab/orangecrab.sh
%%DATADIR%%/frameworks/boards/orangecrab/orangecrab.v
%%DATADIR%%/frameworks/boards/orangecrab/pinout.lpf
%%DATADIR%%/frameworks/boards/riegel/board.json
%%DATADIR%%/frameworks/boards/riegel/riegel.pcf
%%DATADIR%%/frameworks/boards/riegel/riegel.v
%%DATADIR%%/frameworks/boards/techgraph/board.json
%%DATADIR%%/frameworks/boards/techgraph/techgraph.sh
%%DATADIR%%/frameworks/boards/techgraph/techgraph.v
%%DATADIR%%/frameworks/boards/ulx3s/board.json
%%DATADIR%%/frameworks/boards/ulx3s/ulx3s.lpf
%%DATADIR%%/frameworks/boards/ulx3s/ulx3s.sh
%%DATADIR%%/frameworks/boards/ulx3s/ulx3s.v
%%DATADIR%%/frameworks/boards/verilator/board.json
%%DATADIR%%/frameworks/boards/verilator/verilator.sh
%%DATADIR%%/frameworks/boards/verilator/verilator.v
%%DATADIR%%/frameworks/libraries/memory_ports.si
%%DATADIR%%/frameworks/libraries/riscv/ice-v-dual/config_c.ld
%%DATADIR%%/frameworks/libraries/riscv/ice-v-dual/crt0.s
%%DATADIR%%/frameworks/libraries/riscv/ice-v-dual/header.h
%%DATADIR%%/frameworks/libraries/riscv/ice-v-dual/riscv-soc.si
%%DATADIR%%/frameworks/libraries/riscv/ice-v/config_c.ld
%%DATADIR%%/frameworks/libraries/riscv/ice-v/crt0.s
%%DATADIR%%/frameworks/libraries/riscv/ice-v/header.h
%%DATADIR%%/frameworks/libraries/riscv/ice-v/riscv-soc.si
%%DATADIR%%/frameworks/libraries/riscv/riscv-compile.lua
%%DATADIR%%/frameworks/templates/bram_generic.v.in
%%DATADIR%%/frameworks/templates/bram_wmask_byte.v.in
%%DATADIR%%/frameworks/templates/brom_generic.v.in
%%DATADIR%%/frameworks/templates/dualport_bram_altera.v.in
%%DATADIR%%/frameworks/templates/dualport_bram_generic.v.in
%%DATADIR%%/frameworks/templates/dualport_bram_wmask_byte.v.in
%%DATADIR%%/frameworks/templates/simple_dualport_bram_generic.v.in
%%DATADIR%%/frameworks/templates/simple_dualport_bram_wmask_byte.v.in
%%DATADIR%%/frameworks/templates/simple_dualport_bram_wmask_half_bytes.v.in
%%DATADIR%%/frameworks/verilator/README.md
%%DATADIR%%/frameworks/verilator/SPIScreen.cpp
%%DATADIR%%/frameworks/verilator/SPIScreen.h
%%DATADIR%%/frameworks/verilator/VgaChip.cpp
%%DATADIR%%/frameworks/verilator/VgaChip.h
%%DATADIR%%/frameworks/verilator/display.cpp
%%DATADIR%%/frameworks/verilator/display.h
%%DATADIR%%/frameworks/verilator/flyover_simul.gif
%%DATADIR%%/frameworks/verilator/sdr_sdram.cpp
%%DATADIR%%/frameworks/verilator/sdr_sdram.h
%%DATADIR%%/frameworks/verilator/verilator_bare.cpp
%%DATADIR%%/frameworks/verilator/verilator_data.cpp
%%DATADIR%%/frameworks/verilator/verilator_data.h
%%DATADIR%%/frameworks/verilator/verilator_sdram.cpp
%%DATADIR%%/frameworks/verilator/verilator_spiscreen.cpp
%%DATADIR%%/frameworks/verilator/verilator_vga.cpp
%%DATADIR%%/frameworks/verilator/verilator_vga_sdram.cpp