- Update to 3.221
PR: 140231 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br> (maintainer)
This commit is contained in:
parent
ffb2bf0b76
commit
cdd7d962f8
Notes:
svn2git
2021-03-31 03:12:20 +00:00
svn path=/head/; revision=243787
@ -1,12 +1,12 @@
|
||||
# New ports collection makefile for: Verilog-Perl
|
||||
# Date created: 11 Apr 2009
|
||||
# Whom: Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
|
||||
# New ports collection makefile for: Verilog-Perl
|
||||
# Date created: 11 Apr 2009
|
||||
# Whom: Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
PORTNAME= Verilog-Perl
|
||||
PORTVERSION= 3.212
|
||||
PORTVERSION= 3.221
|
||||
CATEGORIES= cad perl5
|
||||
MASTER_SITES= CPAN
|
||||
PKGNAMEPREFIX= p5-
|
||||
@ -30,6 +30,7 @@ MAN3= Verilog::EditFiles.3 Verilog::Netlist::Logger.3 \
|
||||
Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
|
||||
Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 \
|
||||
Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
|
||||
Verilog::Netlist::ContAssign.3 \
|
||||
Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
|
||||
|
||||
.include <bsd.port.pre.mk>
|
||||
|
@ -1,3 +1,3 @@
|
||||
MD5 (Verilog-Perl-3.212.tar.gz) = 5682e42a4904d41206782128b174a7d1
|
||||
SHA256 (Verilog-Perl-3.212.tar.gz) = 8d6829d1062bfd7a343df27c1efeb15a2e79abfc17bafb5e3e8acdf989ad3fd0
|
||||
SIZE (Verilog-Perl-3.212.tar.gz) = 203811
|
||||
MD5 (Verilog-Perl-3.221.tar.gz) = 75f43ca63bcbe927efeabc80830c8dbd
|
||||
SHA256 (Verilog-Perl-3.221.tar.gz) = 443b4875416592b4d1c12652b1507fe78f4123f94951fd30fdabea6e674c4e3f
|
||||
SIZE (Verilog-Perl-3.221.tar.gz) = 210188
|
||||
|
@ -15,6 +15,7 @@ bin/vrename
|
||||
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Pin.pm
|
||||
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Port.pm
|
||||
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Subclass.pm
|
||||
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
|
||||
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Parser.pm
|
||||
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Preproc.pm
|
||||
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/SigParser.pm
|
||||
|
Loading…
Reference in New Issue
Block a user