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cad/verilator: Update 4.038 -> 4.040

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Taking maintainership based on the maintainer's request.

PR:		248713
Approved by:	kevinz5000@gmail.com (maintainer)
This commit is contained in:
Yuri Victorovich 2020-08-18 17:56:39 +00:00
parent cf91f2edba
commit a9f7cc5505
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=545241
2 changed files with 5 additions and 5 deletions
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4
cad/verilator/Makefile
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@ -1,14 +1,14 @@
# $FreeBSD$
PORTNAME= verilator
DISTVERSION= 4.038
DISTVERSION= 4.040
CATEGORIES= cad
MASTER_SITES= https://www.veripool.org/ftp/
PATCH_SITES= https://github.com/${PORTNAME}/${PORTNAME}/commit/
PATCHFILES+= 39f16fb155b9e909f919a9d4ae06890395987b16.patch:-p1 # https://github.com/verilator/verilator/pull/2353
MAINTAINER= kevinz5000@gmail.com
MAINTAINER= yuri@FreeBSD.org
COMMENT= Synthesizable Verilog to C++ compiler
LICENSE= GPLv3

6
cad/verilator/distinfo
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@ -1,5 +1,5 @@
TIMESTAMP = 1595108832
SHA256 (verilator-4.038.tgz) = fa004493216034ac3e26b21b814441bd5801592f4f269c5a4672e3351d73b515
SIZE (verilator-4.038.tgz) = 2703465
TIMESTAMP = 1597706592
SHA256 (verilator-4.040.tgz) = 6e1574924083922a4eb80ff22eedc866f4ce54e5fd6a34101b6af7aa29e5c0e3
SIZE (verilator-4.040.tgz) = 2720606
SHA256 (39f16fb155b9e909f919a9d4ae06890395987b16.patch) = 266c63d54bc00d4a67163b701a10cf238faf9c21f04e0c8192bd5495ff000b80
SIZE (39f16fb155b9e909f919a9d4ae06890395987b16.patch) = 590