- Update to version 20040220

PR: ports/64432 Submitted by: maintainer
svn path=/head/; revision=104546
2004-03-18 22:19:00 +00:00 · 2004-03-18 22:19:00 +00:00 · a0d455de93 · 2021-03-31 03:12:20 +00:00
commit a0d455de93
parent f1f3aad0f7
2 changed files with 4 additions and 4 deletions
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@ -7,11 +7,10 @@
 #

 PORTNAME=	iverilog
-PORTVERSION=	0.7.20031202
-PORTREVISION=	1
+PORTVERSION=	0.7.20040220
 CATEGORIES=	cad
 MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/snapshots/
-DISTNAME=	verilog-20031202
+DISTNAME=	verilog-20040220

 MAINTAINER=	watchman@ludd.luth.se
 COMMENT=	A Verilog simulation and synthesis tool
--- a/cad/iverilog/distinfo
+++ b/cad/iverilog/distinfo
@ -1 +1,2 @@
-MD5 (verilog-20031202.tar.gz) = 14401d3da60ee3da3043523684fbb442
+MD5 (verilog-20040220.tar.gz) = 208d579866e9904a385296220104dcb2
+SIZE (verilog-20040220.tar.gz) = 1354505