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- Update to 3.251

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PR:		ports/148726
Submitted by:	Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br> (maintainer)
This commit is contained in:
Sylvio Cesar Teixeira 2010-07-23 14:33:24 +00:00
parent c5008d1f0f
commit 913a43d5b5
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=258101
3 changed files with 9 additions and 7 deletions
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6
cad/p5-Verilog-Perl/Makefile
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@ -6,7 +6,7 @@
#
PORTNAME= Verilog-Perl
PORTVERSION= 3.223
PORTVERSION= 3.251
CATEGORIES= cad perl5
MASTER_SITES= CPAN
PKGNAMEPREFIX= p5-
@ -28,9 +28,9 @@ MAN3= Verilog::EditFiles.3 Verilog::Netlist::Logger.3 \
Verilog::Parser.3 Verilog::Getopt.3 Verilog::Netlist::Module.3 \
Verilog::Preproc.3 Verilog::Language.3 Verilog::Netlist::Net.3 \
Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 \
Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 Verilog::Netlist::Defparam.3 \
Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
Verilog::Netlist::ContAssign.3 \
Verilog::Netlist::ContAssign.3 Verilog::Netlist::ModPort.3 \
Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
.include <bsd.port.pre.mk>

6
cad/p5-Verilog-Perl/distinfo
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@ -1,3 +1,3 @@
MD5 (Verilog-Perl-3.223.tar.gz) = 54405173d5796dc8dee6a630ae1583c2
SHA256 (Verilog-Perl-3.223.tar.gz) = 9dc9a42938173580c8cbf5bb46760de53d950f3d2f44ceb3c4d6cad787443df6
SIZE (Verilog-Perl-3.223.tar.gz) = 212651
MD5 (Verilog-Perl-3.251.tar.gz) = ff7bbae6e7d2c3e8c8e1f7eee948b08e
SHA256 (Verilog-Perl-3.251.tar.gz) = ee4742c36f84a6170340a1c79b5e5ebaa230d2fb08f85edde479dfd56cd0b708
SIZE (Verilog-Perl-3.251.tar.gz) = 232475

4
cad/p5-Verilog-Perl/pkg-plist
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@ -7,15 +7,17 @@ bin/vrename
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Language.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Cell.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Defparam.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/File.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Interface.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Logger.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ModPort.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Module.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Net.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Pin.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Port.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Subclass.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Parser.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Preproc.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/SigParser.pm