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New port: cad/qflow: End-to-end digital synthesis flow for ASIC designs

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This commit is contained in:
Yuri Victorovich 2020-03-22 10:02:44 +00:00
parent fb4f343c24
commit 647c9273f1
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=528909
8 changed files with 197 additions and 0 deletions
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1
cad/Makefile
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@ -91,6 +91,7 @@
SUBDIR += python-gdsii
SUBDIR += qcad
SUBDIR += qelectrotech
SUBDIR += qflow
SUBDIR += qmls
SUBDIR += qrouter
SUBDIR += repsnapper

34
cad/qflow/Makefile Normal file
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@ -0,0 +1,34 @@
# $FreeBSD$
PORTNAME= qflow
DISTVERSION= 1.4.79
CATEGORIES= cad
MAINTAINER= yuri@FreeBSD.org
COMMENT= End-to-end digital synthesis flow for ASIC designs
LICENSE= GPLv2
APP_DEPENDS= magic>0:cad/magic \
netgen-lvs>0:cad/netgen-lvs \
qrouter>0:cad/qrouter \
yosys>0:cad/yosys
BUILD_DEPENDS= ${APP_DEPENDS}
RUN_DEPENDS= ${APP_DEPENDS}
USES= gmake python tar:tgz tcl tk
USE_GITHUB= yes
GH_ACCOUNT= RTimothyEdwards
GNU_CONFIGURE= yes
post-patch:
@${REINPLACE_CMD} -e 's|^#!ENV_PATH python3$$|#!${PYTHON_CMD}|' ${WRKSRC}/scripts/*.py.in
@${REINPLACE_CMD} -e 's|^#!TCLSH_PATH$$|#!${TCLSH}|' ${WRKSRC}/scripts/*.tcl.in
post-install:
@cd ${STAGEDIR}${PREFIX}/share/qflow/bin && \
${STRIP_CMD} a* b* D* r* s* v* && \
${RM} yosys-abc && ${LN} -s ${LOCALBASE}/bin/abc yosys-abc # https://github.com/RTimothyEdwards/qflow/issues/6
.include <bsd.port.mk>

3
cad/qflow/distinfo Normal file
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@ -0,0 +1,3 @@
TIMESTAMP = 1584862088
SHA256 (RTimothyEdwards-qflow-1.4.79_GH0.tar.gz) = 34328bad0412d6735ba410f9fd03571f614368173de7db01f11e8044f7836174
SIZE (RTimothyEdwards-qflow-1.4.79_GH0.tar.gz) = 939727

11
cad/qflow/files/patch-src_hash.c Normal file
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@ -0,0 +1,11 @@
--- src/hash.c.orig 2020-03-19 05:26:09 UTC
+++ src/hash.c
@@ -19,7 +19,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Camb
#include <stdio.h>
#include <string.h> /* For strdup() */
-#ifdef __APPLE__
+#if defined(__APPLE__) || defined(__FreeBSD__) || defined(__DragonFly__)
#include <stdlib.h>
#else
#include <malloc.h>

11
cad/qflow/files/patch-src_lef.h Normal file
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@ -0,0 +1,11 @@
--- src/lef.h.orig 2020-03-19 05:44:48 UTC
+++ src/lef.h
@@ -28,7 +28,7 @@ typedef unsigned long u_long;
#endif /* _SYS_TYPES_H */
/* Compare functions aren't defined in the Mac's standard library */
-#if defined(__APPLE__)
+#if defined(__APPLE__) || defined(__FreeBSD__) || defined(__DragonFly__)
typedef int (*__compar_fn_t)(const void*, const void*);
#endif

11
cad/qflow/files/patch-src_vesta.c Normal file
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@ -0,0 +1,11 @@
--- src/vesta.c.orig 2020-03-19 05:46:20 UTC
+++ src/vesta.c
@@ -82,7 +82,7 @@
#define LIB_LINE_MAX 65535
-#ifdef __APPLE__
+#if defined(__APPLE__) || defined(__FreeBSD__) || defined(__DragonFly__)
// Linux defines a comparison function prototype, the Mac doesn't. . .
typedef int (*__compar_fn_t)(const void *, const void *);
#endif

11
cad/qflow/pkg-descr Normal file
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@ -0,0 +1,11 @@
A digital synthesis flow is a set of tools and methods used to turn a circuit
design written in a high-level behavioral language like verilog or VHDL into a
physical circuit, which can either be configuration code for an FPGA target like
a Xilinx or Altera chip, or a layout in a specific fabrication process
technology, that would become part of a fabricated circuit chip. Several digital
synthesis flows targeting FPGAs are available, usually from the FPGA
manufacturers, and while they are typically not open source, they are generally
distributed for free (presumably on the sensible assumption that more people
will be buying more FPGA hardware).
WWW: http://opencircuitdesign.com/qflow/

115
cad/qflow/pkg-plist Normal file
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@ -0,0 +1,115 @@
bin/qflow
%%DATADIR%%/bin/DEF2Verilog
%%DATADIR%%/bin/addspacers
%%DATADIR%%/bin/blif2BSpice
%%DATADIR%%/bin/blif2Verilog
%%DATADIR%%/bin/blifFanout
%%DATADIR%%/bin/magic
%%DATADIR%%/bin/netgen
%%DATADIR%%/bin/qrouter
%%DATADIR%%/bin/rc2dly
%%DATADIR%%/bin/spice2delay
%%DATADIR%%/bin/vesta
%%DATADIR%%/bin/vlog2Cel
%%DATADIR%%/bin/vlog2Def
%%DATADIR%%/bin/vlog2Spice
%%DATADIR%%/bin/vlog2Verilog
%%DATADIR%%/bin/vlogFanout
%%DATADIR%%/bin/yosys
%%DATADIR%%/bin/yosys-abc
%%DATADIR%%/scripts/addspacers.tcl
%%DATADIR%%/scripts/annotate.tcl
%%DATADIR%%/scripts/arrangepins.tcl
%%DATADIR%%/scripts/blif2cel.tcl
%%DATADIR%%/scripts/blifanno.tcl
%%DATADIR%%/scripts/checkdirs.sh
%%DATADIR%%/scripts/cleanup.sh
%%DATADIR%%/scripts/consoletext.py
%%DATADIR%%/scripts/count_lvs.py
%%DATADIR%%/scripts/decongest.tcl
%%DATADIR%%/scripts/getantennacell.tcl
%%DATADIR%%/scripts/getfillcell.tcl
%%DATADIR%%/scripts/getpowerground.tcl
%%DATADIR%%/scripts/graywolf.sh
%%DATADIR%%/scripts/helpwindow.py
%%DATADIR%%/scripts/magic_db.sh
%%DATADIR%%/scripts/magic_drc.sh
%%DATADIR%%/scripts/magic_gds.sh
%%DATADIR%%/scripts/magic_view.sh
%%DATADIR%%/scripts/netgen_lvs.sh
%%DATADIR%%/scripts/opensta.sh
%%DATADIR%%/scripts/opentimer.sh
%%DATADIR%%/scripts/pinmanager.py
%%DATADIR%%/scripts/place2def.tcl
%%DATADIR%%/scripts/place2lef2.tcl
%%DATADIR%%/scripts/place2net2.tcl
%%DATADIR%%/scripts/powerbus.tcl
%%DATADIR%%/scripts/preproc.py
%%DATADIR%%/scripts/qflow.sh
%%DATADIR%%/scripts/qflow_help.txt
%%DATADIR%%/scripts/qflow_manager.py
%%DATADIR%%/scripts/qrouter.sh
%%DATADIR%%/scripts/removeblocks.tcl
%%DATADIR%%/scripts/replace.sh
%%DATADIR%%/scripts/spi2xspice.py
%%DATADIR%%/scripts/textreport.py
%%DATADIR%%/scripts/tksimpledialog.py
%%DATADIR%%/scripts/tooltip.py
%%DATADIR%%/scripts/vesta.sh
%%DATADIR%%/scripts/ybuffer.tcl
%%DATADIR%%/scripts/yosys.sh
%%DATADIR%%/scripts/ypostproc.tcl
%%DATADIR%%/tech/gscl45nm/gscl45nm.gds
%%DATADIR%%/tech/gscl45nm/gscl45nm.lef
%%DATADIR%%/tech/gscl45nm/gscl45nm.lib
%%DATADIR%%/tech/gscl45nm/gscl45nm.magicrc
%%DATADIR%%/tech/gscl45nm/gscl45nm.par
%%DATADIR%%/tech/gscl45nm/gscl45nm.prm
%%DATADIR%%/tech/gscl45nm/gscl45nm.sh
%%DATADIR%%/tech/gscl45nm/gscl45nm.sp
%%DATADIR%%/tech/gscl45nm/gscl45nm.tech
%%DATADIR%%/tech/gscl45nm/gscl45nm.v
%%DATADIR%%/tech/gscl45nm/gscl45nm_setup.tcl
%%DATADIR%%/tech/osu018/SCN6M_SUBM.10.tech
%%DATADIR%%/tech/osu018/osu018.magicrc
%%DATADIR%%/tech/osu018/osu018.par
%%DATADIR%%/tech/osu018/osu018.prm
%%DATADIR%%/tech/osu018/osu018.sh
%%DATADIR%%/tech/osu018/osu018_setup.tcl
%%DATADIR%%/tech/osu018/osu018_stdcells.gds2
%%DATADIR%%/tech/osu018/osu018_stdcells.lef
%%DATADIR%%/tech/osu018/osu018_stdcells.lib
%%DATADIR%%/tech/osu018/osu018_stdcells.sp
%%DATADIR%%/tech/osu018/osu018_stdcells.v
%%DATADIR%%/tech/osu035/SCN4M_SUBM.20.tech
%%DATADIR%%/tech/osu035/osu035.magicrc
%%DATADIR%%/tech/osu035/osu035.par
%%DATADIR%%/tech/osu035/osu035.prm
%%DATADIR%%/tech/osu035/osu035.sh
%%DATADIR%%/tech/osu035/osu035_setup.tcl
%%DATADIR%%/tech/osu035/osu035_stdcells.gds2
%%DATADIR%%/tech/osu035/osu035_stdcells.lef
%%DATADIR%%/tech/osu035/osu035_stdcells.lib
%%DATADIR%%/tech/osu035/osu035_stdcells.sp
%%DATADIR%%/tech/osu035/osu035_stdcells.v
%%DATADIR%%/tech/osu035_redm4/osu035.prm
%%DATADIR%%/tech/osu035_redm4/osu035_redm4.magicrc
%%DATADIR%%/tech/osu035_redm4/osu035_redm4.par
%%DATADIR%%/tech/osu035_redm4/osu035_redm4.sh
%%DATADIR%%/tech/osu035_redm4/osu035_redm4_setup.tcl
%%DATADIR%%/tech/osu035_redm4/osu035_redm4_stdcells.lef
%%DATADIR%%/tech/osu035_redm4/osu035_stdcells.gds2
%%DATADIR%%/tech/osu035_redm4/osu035_stdcells.lib
%%DATADIR%%/tech/osu035_redm4/osu035_stdcells.sp
%%DATADIR%%/tech/osu035_redm4/osu035_stdcells.v
%%DATADIR%%/tech/osu050/SCN3ME_SUBM.30.tech
%%DATADIR%%/tech/osu050/osu050.magicrc
%%DATADIR%%/tech/osu050/osu050.par
%%DATADIR%%/tech/osu050/osu050.prm
%%DATADIR%%/tech/osu050/osu050.sh
%%DATADIR%%/tech/osu050/osu050_setup.tcl
%%DATADIR%%/tech/osu050/osu050_stdcells.lef
%%DATADIR%%/tech/osu050/osu050_stdcells.sp
%%DATADIR%%/tech/osu050/osu05_stdcells.gds2
%%DATADIR%%/tech/osu050/osu05_stdcells.lib
%%DATADIR%%/tech/osu050/osu05_stdcells.v