Update riscv-isa-sim to 2020-11-02 snapshot

- Switch to the official upstream, github.com/riscv/riscv-isa-sim.
 - Remove emulators/riscv-fesvr, as it is now bundled with Spike.
 - Drop patches.

Submitted by:	lwhsu (earlier version)
Reviewed by:	lwhsu
Approved by:	lwhsu (ports, maintainer)
Differential Revision:	https://reviews.freebsd.org/D27144

MOVED

@@ -15680,3 +15680,4 @@ multimedia/swfdec-gnome||2020-11-09|Depends on the expired gstreamer 0.10
 grapihcs/swfdec||2020-11-09|Depends on the expired gstreamer 0.10
 multimedia/py-openlp||2020-11-09|Depends on the expired gstreamer 0.10
 multimedia/p5-GStreamer||2020-11-09|Depends on the expired gstreamer 0.10
+emulators/riscv-fesvr||2020-11-09|Now bundled with emulators/riscv-isa-sim

emulators/riscv-fesvr/Makefile

@@ -1,37 +0,0 @@
-# $FreeBSD$
-
-PORTNAME=	riscv-fesvr
-DISTVERSION=	git
-PORTREVISION=	20181005
-CATEGORIES=	emulators
-
-MAINTAINER=	lwhsu@FreeBSD.org
-COMMENT=	RISC-V Frontend Server
-
-LICENSE=	BSD3CLAUSE
-
-ONLY_FOR_ARCHS=	amd64
-
-USES=	gmake
-
-GH_ACCOUNT=	freebsd-riscv
-GH_TAGNAME=	8c831dc
-
-HAS_CONFIGURE=	yes
-USE_GITHUB=	yes
-USE_LDCONFIG=	yes
-
-STRIP_FILES=	bin/elf2hex \
-		lib/libfesvr.so
-
-post-patch:
-	${REINPLACE_CMD} -e \
-	's|[(]install_libs_dir[)]/pkgconfig|(INSTALLDIR)/libdata/pkgconfig|g' \
-	${WRKSRC}/Makefile.in
-
-post-install:
-.	for f in ${STRIP_FILES}
-		${STRIP_CMD} ${STAGEDIR}${PREFIX}/${f}
-.	endfor
-
-.include <bsd.port.mk>

emulators/riscv-fesvr/distinfo

@@ -1,3 +0,0 @@
-TIMESTAMP = 1538736336
-SHA256 (freebsd-riscv-riscv-fesvr-git-8c831dc_GH0.tar.gz) = 60a514952642daf532fdb31488f16a34336c301a5f6020ed1558e03bd4e258a9
-SIZE (freebsd-riscv-riscv-fesvr-git-8c831dc_GH0.tar.gz) = 120946

emulators/riscv-fesvr/pkg-descr

@@ -1,7 +0,0 @@
-RISC-V Frontend Server
-
-The RISC-V front-end server library, which facilitates communication between a
-host machine and a RISC-V target machine. It is usually not meant to be used as
-a standalone package.
-
-WWW: https://github.com/freebsd-riscv/riscv-fesvr

emulators/riscv-fesvr/pkg-plist

@@ -1,17 +0,0 @@
-bin/elf2hex
-include/fesvr/context.h
-include/fesvr/device.h
-include/fesvr/dtm.h
-include/fesvr/elf.h
-include/fesvr/elfloader.h
-include/fesvr/htif_hexwriter.h
-include/fesvr/htif_pthread.h
-include/fesvr/htif.h
-include/fesvr/memif.h
-include/fesvr/option_parser.h
-include/fesvr/rfb.h
-include/fesvr/syscall.h
-include/fesvr/term.h
-include/fesvr/tsi.h
-lib/libfesvr.so
-libdata/pkgconfig/riscv-fesvr.pc

emulators/riscv-isa-sim/Makefile

@@ -2,7 +2,7 @@
 
 PORTNAME=	riscv-isa-sim
 DISTVERSION=	git
-PORTREVISION=	20181007
+PORTREVISION=	20201102
 CATEGORIES=	emulators
 
 MAINTAINER=	lwhsu@FreeBSD.org
@@ -12,33 +12,27 @@ LICENSE=	BSD3CLAUSE
 
 ONLY_FOR_ARCHS=	amd64
 
-LIB_DEPENDS=	libfesvr.so:emulators/riscv-fesvr
-
 USES=	compiler:c++11-lang gmake shebangfix
 
-GH_ACCOUNT=	freebsd-riscv
+GH_ACCOUNT=	riscv
-GH_TAGNAME=	aae60e0
+GH_TAGNAME=	641d7d0
 
 HAS_CONFIGURE=	yes
 SHEBANG_FILES=	scripts/vcs-version.sh
+
 USE_GITHUB=	yes
 USE_LDCONFIG=	yes
 
-LDFLAGS+=	-L${LOCALBASE}/lib
+CFLAGS+=	-DRISCV_ENABLE_DIRTY=1
-CFLAGS+=	-I${LOCALBASE}/include \
-		-DRISCV_ENABLE_DIRTY=1
 
-STRIP_FILES=	bin/spike \
+STRIP_FILES=	bin/elf2hex \
+		bin/spike \
 		bin/spike-dasm \
+		bin/spike-log-parser \
 		bin/termios-xspike \
 		bin/xspike \
-		lib/libdummy_rocc.so \
+		lib/libcustomext.so \
-		lib/libriscv.so \
+		lib/libsoftfloat.so
-		lib/libsoftfloat.so \
-		lib/libspike_main.so
-
-post-extract:
-	@${MV} ${WRKSRC}/riscv/insn_template.h ${WRKSRC}/riscv/insn_template.hpp
 
 post-patch:
 	${REINPLACE_CMD} -e \

emulators/riscv-isa-sim/distinfo

@@ -1,3 +1,3 @@
-TIMESTAMP = 1538736497
+TIMESTAMP = 1604881926
-SHA256 (freebsd-riscv-riscv-isa-sim-git-aae60e0_GH0.tar.gz) = 423005144e71b272fad7f13b57af7de561a178af096a71d304e0a3c590520195
+SHA256 (riscv-riscv-isa-sim-git-641d7d0_GH0.tar.gz) = 810c0567ba31459a37bd84498071c68b1a85b8dc7f891df800b02201544e5149
-SIZE (freebsd-riscv-riscv-isa-sim-git-aae60e0_GH0.tar.gz) = 232817
+SIZE (riscv-riscv-isa-sim-git-641d7d0_GH0.tar.gz) = 385330

emulators/riscv-isa-sim/files/patch-Makefile.in

@@ -1,19 +0,0 @@
---- Makefile.in.orig	2018-10-05 10:52:51 UTC
-+++ Makefile.in
-@@ -187,13 +187,13 @@ _$(1).cc :
- 
- # Build the object files for this subproject
- 
--$(2)_pch := $$(patsubst %.h, %.h.gch, $$($(2)_precompiled_hdrs))
-+$(2)_pch := $$(patsubst %.hpp, %.h.gch, $$($(2)_precompiled_hdrs))
- $(2)_objs := $$(patsubst %.cc, %.o, $$($(2)_srcs))
- $(2)_c_objs := $$(patsubst %.c, %.o, $$($(2)_c_srcs))
- $(2)_deps := $$(patsubst %.o, %.d, $$($(2)_objs))
- $(2)_deps += $$(patsubst %.o, %.d, $$($(2)_c_objs))
--$(2)_deps += $$(patsubst %.h, %.h.d, $$($(2)_precompiled_hdrs))
--$$($(2)_pch) : %.h.gch : %.h
-+$(2)_deps += $$(patsubst %.hpp, %.h.d, $$($(2)_precompiled_hdrs))
-+$$($(2)_pch) : %.h.gch : %.hpp
- 	$(COMPILE) -x c++-header $$< -o $$@
- # If using clang, don't depend (and thus don't build) precompiled headers
- $$($(2)_objs) : %.o : %.cc $$($(2)_gen_hdrs) $(if $(filter-out clang,$(CC)),$$($(2)_pch))

emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc

@@ -1,10 +0,0 @@
---- riscv/insn_template.cc.orig	2018-10-05 10:52:33 UTC
-+++ riscv/insn_template.cc
-@@ -1,6 +1,6 @@
- // See LICENSE for license details.
- 
--#include "insn_template.h"
-+#include "insn_template.hpp"
- 
- reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc)
- {

emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in

@@ -1,20 +0,0 @@
---- riscv/riscv.mk.in.orig	2018-10-05 10:52:11 UTC
-+++ riscv/riscv.mk.in
-@@ -23,7 +23,7 @@ riscv_hdrs = \
- 	tracer.h \
- 	extension.h \
- 	rocc.h \
--	insn_template.h \
-+	insn_template.hpp \
- 	mulhi.h \
- 	debug_module.h \
- 	debug_rom_defines.h \
-@@ -31,7 +31,7 @@ riscv_hdrs = \
- 	jtag_dtm.h \
- 
- riscv_precompiled_hdrs = \
--	insn_template.h \
-+	insn_template.hpp \
- 
- riscv_srcs = \
- 	processor.cc \

emulators/riscv-isa-sim/pkg-descr

@@ -3,4 +3,4 @@ Spike, a RISC-V ISA Simulator
 The RISC-V ISA Simulator implements a functional model of one or more RISC-V
 processors.
 
-WWW: https://github.com/freebsd-riscv/riscv-isa-sim
+WWW: https://github.com/riscv/riscv-isa-sim

emulators/riscv-isa-sim/pkg-plist

@@ -1,44 +1,27 @@
+bin/elf2hex
 bin/spike
 bin/spike-dasm
+bin/spike-log-parser
 bin/termios-xspike
 bin/xspike
-include/spike/cachesim.h
+include/fesvr/context.h
-include/spike/common.h
+include/fesvr/device.h
-include/spike/config.h
+include/fesvr/dtm.h
-include/spike/debug_module.h
+include/fesvr/elf.h
-include/spike/debug_rom_defines.h
+include/fesvr/elfloader.h
-include/spike/decode.h
+include/fesvr/htif.h
-include/spike/devices.h
+include/fesvr/htif_hexwriter.h
-include/spike/disasm.h
+include/fesvr/htif_pthread.h
-include/spike/dts.h
+include/fesvr/memif.h
-include/spike/encoding.h
+include/fesvr/option_parser.h
-include/spike/extension.h
+include/fesvr/rfb.h
-include/spike/icache.h
+include/fesvr/syscall.h
-include/spike/insn_list.h
+include/fesvr/term.h
-include/spike/insn_template.hpp
+include/fesvr/tsi.h
-include/spike/internals.h
+include/riscv/mmio_plugin.h
-include/spike/jtag_dtm.h
+lib/libcustomext.so
-include/spike/memtracer.h
+lib/libdisasm.a
-include/spike/mmu.h
+lib/libfesvr.a
-include/spike/mulhi.h
-include/spike/platform.h
-include/spike/primitiveTypes.h
-include/spike/primitives.h
-include/spike/processor.h
-include/spike/remote_bitbang.h
-include/spike/rocc.h
-include/spike/sim.h
-include/spike/simif.h
-include/spike/softfloat.h
-include/spike/softfloat_types.h
-include/spike/specialize.h
-include/spike/tracer.h
-include/spike/trap.h
-lib/libdummy_rocc.so
-lib/libriscv.so
 lib/libsoftfloat.so
-lib/libspike_main.so
+libdata/pkgconfig/riscv-disasm.pc
-libdata/pkgconfig/riscv-dummy_rocc.pc
+libdata/pkgconfig/riscv-fesvr.pc
-libdata/pkgconfig/riscv-riscv.pc
-libdata/pkgconfig/riscv-softfloat.pc
-libdata/pkgconfig/riscv-spike_main.pc