Update riscv-isa-sim to 2020-11-02 snapshot
- Switch to the official upstream, github.com/riscv/riscv-isa-sim. - Remove emulators/riscv-fesvr, as it is now bundled with Spike. - Drop patches. Submitted by: lwhsu (earlier version) Reviewed by: lwhsu Approved by: lwhsu (ports, maintainer) Differential Revision: https://reviews.freebsd.org/D27144
This commit is contained in:
Mitchell Horne
parent
d1682723a1
commit
4049e5046c
Notes:
svn2git
2021-03-31 03:12:20 +00:00
svn path=/head/; revision=554722
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@ -15680,3 +15680,4 @@ multimedia/swfdec-gnome||2020-11-09|Depends on the expired gstreamer 0.10
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grapihcs/swfdec||2020-11-09|Depends on the expired gstreamer 0.10
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multimedia/py-openlp||2020-11-09|Depends on the expired gstreamer 0.10
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multimedia/p5-GStreamer||2020-11-09|Depends on the expired gstreamer 0.10
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emulators/riscv-fesvr||2020-11-09|Now bundled with emulators/riscv-isa-sim
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@ -1,37 +0,0 @@
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# $FreeBSD$
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PORTNAME= riscv-fesvr
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DISTVERSION= git
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PORTREVISION= 20181005
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CATEGORIES= emulators
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MAINTAINER= lwhsu@FreeBSD.org
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COMMENT= RISC-V Frontend Server
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LICENSE= BSD3CLAUSE
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ONLY_FOR_ARCHS= amd64
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USES= gmake
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GH_ACCOUNT= freebsd-riscv
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GH_TAGNAME= 8c831dc
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HAS_CONFIGURE= yes
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USE_GITHUB= yes
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USE_LDCONFIG= yes
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STRIP_FILES= bin/elf2hex \
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lib/libfesvr.so
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post-patch:
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${REINPLACE_CMD} -e \
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's|[(]install_libs_dir[)]/pkgconfig|(INSTALLDIR)/libdata/pkgconfig|g' \
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${WRKSRC}/Makefile.in
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post-install:
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. for f in ${STRIP_FILES}
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${STRIP_CMD} ${STAGEDIR}${PREFIX}/${f}
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. endfor
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.include <bsd.port.mk>
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@ -1,3 +0,0 @@
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TIMESTAMP = 1538736336
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SHA256 (freebsd-riscv-riscv-fesvr-git-8c831dc_GH0.tar.gz) = 60a514952642daf532fdb31488f16a34336c301a5f6020ed1558e03bd4e258a9
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SIZE (freebsd-riscv-riscv-fesvr-git-8c831dc_GH0.tar.gz) = 120946
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@ -1,7 +0,0 @@
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RISC-V Frontend Server
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The RISC-V front-end server library, which facilitates communication between a
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host machine and a RISC-V target machine. It is usually not meant to be used as
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a standalone package.
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WWW: https://github.com/freebsd-riscv/riscv-fesvr
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@ -1,17 +0,0 @@
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bin/elf2hex
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include/fesvr/context.h
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include/fesvr/device.h
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include/fesvr/dtm.h
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include/fesvr/elf.h
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include/fesvr/elfloader.h
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include/fesvr/htif_hexwriter.h
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include/fesvr/htif_pthread.h
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include/fesvr/htif.h
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include/fesvr/memif.h
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include/fesvr/option_parser.h
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include/fesvr/rfb.h
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include/fesvr/syscall.h
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include/fesvr/term.h
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include/fesvr/tsi.h
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lib/libfesvr.so
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libdata/pkgconfig/riscv-fesvr.pc
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@ -2,7 +2,7 @@
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PORTNAME= riscv-isa-sim
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DISTVERSION= git
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PORTREVISION= 20181007
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PORTREVISION= 20201102
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CATEGORIES= emulators
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MAINTAINER= lwhsu@FreeBSD.org
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@ -12,33 +12,27 @@ LICENSE= BSD3CLAUSE
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ONLY_FOR_ARCHS= amd64
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LIB_DEPENDS= libfesvr.so:emulators/riscv-fesvr
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USES= compiler:c++11-lang gmake shebangfix
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GH_ACCOUNT= freebsd-riscv
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GH_TAGNAME= aae60e0
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GH_ACCOUNT= riscv
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GH_TAGNAME= 641d7d0
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HAS_CONFIGURE= yes
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SHEBANG_FILES= scripts/vcs-version.sh
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USE_GITHUB= yes
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USE_LDCONFIG= yes
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LDFLAGS+= -L${LOCALBASE}/lib
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CFLAGS+= -I${LOCALBASE}/include \
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-DRISCV_ENABLE_DIRTY=1
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CFLAGS+= -DRISCV_ENABLE_DIRTY=1
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STRIP_FILES= bin/spike \
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STRIP_FILES= bin/elf2hex \
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bin/spike \
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bin/spike-dasm \
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bin/spike-log-parser \
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bin/termios-xspike \
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bin/xspike \
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lib/libdummy_rocc.so \
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lib/libriscv.so \
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lib/libsoftfloat.so \
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lib/libspike_main.so
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post-extract:
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@${MV} ${WRKSRC}/riscv/insn_template.h ${WRKSRC}/riscv/insn_template.hpp
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lib/libcustomext.so \
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lib/libsoftfloat.so
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post-patch:
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${REINPLACE_CMD} -e \
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@ -1,3 +1,3 @@
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TIMESTAMP = 1538736497
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SHA256 (freebsd-riscv-riscv-isa-sim-git-aae60e0_GH0.tar.gz) = 423005144e71b272fad7f13b57af7de561a178af096a71d304e0a3c590520195
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SIZE (freebsd-riscv-riscv-isa-sim-git-aae60e0_GH0.tar.gz) = 232817
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TIMESTAMP = 1604881926
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SHA256 (riscv-riscv-isa-sim-git-641d7d0_GH0.tar.gz) = 810c0567ba31459a37bd84498071c68b1a85b8dc7f891df800b02201544e5149
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SIZE (riscv-riscv-isa-sim-git-641d7d0_GH0.tar.gz) = 385330
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@ -1,19 +0,0 @@
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--- Makefile.in.orig 2018-10-05 10:52:51 UTC
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+++ Makefile.in
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@@ -187,13 +187,13 @@ _$(1).cc :
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# Build the object files for this subproject
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-$(2)_pch := $$(patsubst %.h, %.h.gch, $$($(2)_precompiled_hdrs))
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+$(2)_pch := $$(patsubst %.hpp, %.h.gch, $$($(2)_precompiled_hdrs))
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$(2)_objs := $$(patsubst %.cc, %.o, $$($(2)_srcs))
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$(2)_c_objs := $$(patsubst %.c, %.o, $$($(2)_c_srcs))
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$(2)_deps := $$(patsubst %.o, %.d, $$($(2)_objs))
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$(2)_deps += $$(patsubst %.o, %.d, $$($(2)_c_objs))
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-$(2)_deps += $$(patsubst %.h, %.h.d, $$($(2)_precompiled_hdrs))
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-$$($(2)_pch) : %.h.gch : %.h
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+$(2)_deps += $$(patsubst %.hpp, %.h.d, $$($(2)_precompiled_hdrs))
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+$$($(2)_pch) : %.h.gch : %.hpp
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$(COMPILE) -x c++-header $$< -o $$@
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# If using clang, don't depend (and thus don't build) precompiled headers
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$$($(2)_objs) : %.o : %.cc $$($(2)_gen_hdrs) $(if $(filter-out clang,$(CC)),$$($(2)_pch))
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@ -1,10 +0,0 @@
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--- riscv/insn_template.cc.orig 2018-10-05 10:52:33 UTC
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+++ riscv/insn_template.cc
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@@ -1,6 +1,6 @@
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// See LICENSE for license details.
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-#include "insn_template.h"
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+#include "insn_template.hpp"
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reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc)
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{
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@ -1,20 +0,0 @@
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--- riscv/riscv.mk.in.orig 2018-10-05 10:52:11 UTC
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+++ riscv/riscv.mk.in
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@@ -23,7 +23,7 @@ riscv_hdrs = \
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tracer.h \
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extension.h \
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rocc.h \
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- insn_template.h \
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+ insn_template.hpp \
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mulhi.h \
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debug_module.h \
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debug_rom_defines.h \
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@@ -31,7 +31,7 @@ riscv_hdrs = \
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jtag_dtm.h \
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riscv_precompiled_hdrs = \
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- insn_template.h \
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+ insn_template.hpp \
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riscv_srcs = \
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processor.cc \
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@ -3,4 +3,4 @@ Spike, a RISC-V ISA Simulator
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The RISC-V ISA Simulator implements a functional model of one or more RISC-V
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processors.
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WWW: https://github.com/freebsd-riscv/riscv-isa-sim
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WWW: https://github.com/riscv/riscv-isa-sim
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@ -1,44 +1,27 @@
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bin/elf2hex
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bin/spike
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bin/spike-dasm
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bin/spike-log-parser
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bin/termios-xspike
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bin/xspike
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include/spike/cachesim.h
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include/spike/common.h
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include/spike/config.h
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include/spike/debug_module.h
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include/spike/debug_rom_defines.h
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include/spike/decode.h
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include/spike/devices.h
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include/spike/disasm.h
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include/spike/dts.h
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include/spike/encoding.h
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include/spike/extension.h
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include/spike/icache.h
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include/spike/insn_list.h
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include/spike/insn_template.hpp
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include/spike/internals.h
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include/spike/jtag_dtm.h
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include/spike/memtracer.h
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include/spike/mmu.h
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include/spike/mulhi.h
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include/spike/platform.h
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include/spike/primitiveTypes.h
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include/spike/primitives.h
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include/spike/processor.h
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include/spike/remote_bitbang.h
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include/spike/rocc.h
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include/spike/sim.h
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include/spike/simif.h
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include/spike/softfloat.h
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include/spike/softfloat_types.h
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include/spike/specialize.h
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include/spike/tracer.h
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include/spike/trap.h
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lib/libdummy_rocc.so
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lib/libriscv.so
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include/fesvr/context.h
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include/fesvr/device.h
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include/fesvr/dtm.h
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include/fesvr/elf.h
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include/fesvr/elfloader.h
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include/fesvr/htif.h
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include/fesvr/htif_hexwriter.h
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include/fesvr/htif_pthread.h
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include/fesvr/memif.h
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include/fesvr/option_parser.h
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include/fesvr/rfb.h
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include/fesvr/syscall.h
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include/fesvr/term.h
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include/fesvr/tsi.h
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include/riscv/mmio_plugin.h
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lib/libcustomext.so
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lib/libdisasm.a
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lib/libfesvr.a
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lib/libsoftfloat.so
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lib/libspike_main.so
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libdata/pkgconfig/riscv-dummy_rocc.pc
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libdata/pkgconfig/riscv-riscv.pc
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libdata/pkgconfig/riscv-softfloat.pc
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libdata/pkgconfig/riscv-spike_main.pc
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libdata/pkgconfig/riscv-disasm.pc
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libdata/pkgconfig/riscv-fesvr.pc
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