cad/opentimer: New port: High-performance timing analysis tool for VLSI systems

cad/Makefile

@@ -88,6 +88,7 @@
     SUBDIR += openroad
     SUBDIR += openscad
     SUBDIR += openscad-devel
+    SUBDIR += opentimer
     SUBDIR += openvsp
     SUBDIR += oregano
     SUBDIR += p5-GDS2

cad/opentimer/Makefile

@@ -0,0 +1,33 @@
+PORTNAME=	opentimer
+PORTVERSION=	g20210726
+CATEGORIES=	cad
+
+MAINTAINER=	yuri@FreeBSD.org
+COMMENT=	High-performance timing analysis tool for VLSI systems
+
+LICENSE=	MIT
+LICENSE_FILE=	${WRKSRC}/LICENSE
+
+USES=		cmake compiler:c++17-lang tcl
+USE_GCC=	yes # fails to build with clang-11: https://github.com/OpenTimer/OpenTimer/issues/48
+
+USE_GITHUB=	yes
+GH_ACCOUNT=	OpenTimer
+GH_PROJECT=	OpenTimer
+GH_TAGNAME=	18d28ff
+
+PLIST_FILES=	bin/ot-shell \
+		bin/ot-tau15 \
+		bin/ot-tau18 \
+		bin/ot-utility
+
+do-install: # see https://github.com/OpenTimer/OpenTimer/issues/47
+.for e in ot-shell ot-tau15 ot-tau18 ot-utility
+	${INSTALL_PROGRAM} ${WRKSRC}/bin/${e} ${STAGEDIR}${PREFIX}/bin
+.endfor
+
+do-test: # runs the script suggested in https://github.com/OpenTimer/OpenTimer
+	@cd ${WRKSRC} && \
+		bin/ot-shell < ${FILESDIR}/test.txt
+
+.include <bsd.port.mk>

cad/opentimer/distinfo

@@ -0,0 +1,3 @@
+TIMESTAMP = 1631485980
+SHA256 (OpenTimer-OpenTimer-g20210726-18d28ff_GH0.tar.gz) = 17c766c81c086419fc95c24576a511f43b8219d8402f8651d3c942d79bf0f4b4
+SIZE (OpenTimer-OpenTimer-g20210726-18d28ff_GH0.tar.gz) = 120737819

cad/opentimer/files/patch-ot_utility_logger.hpp

@@ -0,0 +1,12 @@
+- workaround for missing S_IRUSR,etc, see https://github.com/OpenTimer/OpenTimer/issues/46
+
+--- ot/utility/logger.hpp.orig	2021-09-12 22:40:42 UTC
++++ ot/utility/logger.hpp
+@@ -13,6 +13,7 @@
+ #include <mutex>
+ #include <fcntl.h>
+ #include <unistd.h>
++#include <sys/stat.h>
+ 
+ namespace ot {
+ 

cad/opentimer/files/test.txt

@@ -0,0 +1,5 @@
+cd example/simple
+read_celllib osu018_stdcells.lib
+read_verilog simple.v   
+read_sdc simple.sdc
+report_timing

cad/opentimer/pkg-descr

@@ -0,0 +1,11 @@
+OpenTimer is a new static timing analysis (STA) tool to help IC designers
+quickly verify the circuit timing. It is developed completely from the ground up
+using C++17 to efficiently support parallel and incremental timing.
+
+Key features are:
+* Industry standard format (.lib, .v, .spef, .sdc) support
+* Graph- and path-based timing analysis
+* Parallel incremental timing for fast timing closure
+* Award-winning tools and golden timers in CAD Contests
+
+WWW: https://github.com/OpenTimer/OpenTimer