13 lines
242 B
Verilog
13 lines
242 B
Verilog
module mapper
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(input [5:0] i_addr,
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output [8:0] o_data);
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reg [8:0] mapping_rom [63:0];
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initial begin
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$readmemh("/Users/car/Projects/hope/umap.hex", mapping_rom);
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end
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assign o_data = mapping_rom[i_addr];
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endmodule
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