19604 lines
328 KiB
HTML
19604 lines
328 KiB
HTML
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
|
<html>
|
|
<head>
|
|
<title>Timing Analysis Report</title>
|
|
<style type="text/css">
|
|
@import url(../temp/style.css);
|
|
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
|
div#content { width: 100%; margin: }
|
|
hr { margin-top: 30px; margin-bottom: 30px; }
|
|
h1, h3 { text-align: center; }
|
|
h1 {margin-top: 50px; }
|
|
table, th, td {white-space:pre; border: 1px solid #aaa; }
|
|
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
|
th, td { padding: 5px 5px 5px 5px; }
|
|
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
|
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
|
table.detail_table th.label { min-width: 8%; width: 8%; }
|
|
</style>
|
|
</head>
|
|
<body>
|
|
<div id="content">
|
|
<h1><a name="Message">Timing Messages</a></h1>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Report Title</td>
|
|
<td>Timing Analysis Report</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Design File</td>
|
|
<td>/Users/car/Projects/hope/hope/impl/gwsynthesis/hope.vg</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Physical Constraints File</td>
|
|
<td>/Users/car/Projects/hope/tangnano20k.cst</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Timing Constraint File</td>
|
|
<td>/Users/car/Projects/hope/tangnano20k.sdc</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Tool Version</td>
|
|
<td>V1.9.11.03 Education</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Part Number</td>
|
|
<td>GW2AR-LV18QN88C8/I7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Device</td>
|
|
<td>GW2AR-18</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Device Version</td>
|
|
<td>C</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Created Time</td>
|
|
<td>Fri Feb 20 01:45:30 2026
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Legal Announcement</td>
|
|
<td>Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.</td>
|
|
</tr>
|
|
</table>
|
|
<h1><a name="Summary">Timing Summaries</a></h1>
|
|
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Setup Delay Model</td>
|
|
<td>Slow 0.95V 85C C8/I7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Delay Model</td>
|
|
<td>Fast 1.05V 0C C8/I7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Numbers of Paths Analyzed</td>
|
|
<td>1081</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Numbers of Endpoints Analyzed</td>
|
|
<td>698</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Numbers of Falling Endpoints</td>
|
|
<td>0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Numbers of Setup Violated Endpoints</td>
|
|
<td>0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Numbers of Hold Violated Endpoints</td>
|
|
<td>0</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Clock_Report">Clock Summary:</a></h2>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">NO.</th>
|
|
<th class="label">Clock Name</th>
|
|
<th class="label">Type</th>
|
|
<th class="label">Period</th>
|
|
<th class="label">Frequency(MHz)</th>
|
|
<th class="label">Rise</th>
|
|
<th class="label">Fall</th>
|
|
<th class="label">Source</th>
|
|
<th class="label">Master</th>
|
|
<th class="label">Objects</th>
|
|
</tr>
|
|
<tr>
|
|
<td>1</td>
|
|
<td>i_clk</td>
|
|
<td>Base</td>
|
|
<td>37.040</td>
|
|
<td>26.998
|
|
<td>0.000</td>
|
|
<td>18.518</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk </td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
|
|
<table>
|
|
<tr>
|
|
<th>NO.</th>
|
|
<th>Clock Name</th>
|
|
<th>Constraint</th>
|
|
<th>Actual Fmax</th>
|
|
<th>Logic Level</th>
|
|
<th>Entity</th>
|
|
</tr>
|
|
<tr>
|
|
<td>1</td>
|
|
<td>i_clk</td>
|
|
<td>26.998(MHz)</td>
|
|
<td>36.912(MHz)</td>
|
|
<td>19</td>
|
|
<td>TOP</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">Clock Name</th>
|
|
<th class="label">Analysis Type</th>
|
|
<th class="label">Endpoints TNS</th>
|
|
<th class="label">Number of Endpoints</th>
|
|
</tr>
|
|
<tr>
|
|
<td>i_clk</td>
|
|
<td>Setup</td>
|
|
<td>0.000</td>
|
|
<td>0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>i_clk</td>
|
|
<td>Hold</td>
|
|
<td>0.000</td>
|
|
<td>0</td>
|
|
</tr>
|
|
</table>
|
|
<h1><a name="Detail">Timing Details</a></h1>
|
|
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
|
|
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
|
|
<h4>Report Command:report_timing -setup -from_clock [get_clocks {i_clk}] -to_clock [get_clocks {i_clk}] -max_paths 25 -max_common_paths 1</h4>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">Path Number</th>
|
|
<th class="label">Path Slack</th>
|
|
<th class="label">From Node</th>
|
|
<th class="label">To Node</th>
|
|
<th class="label">From Clock</th>
|
|
<th class="label">To Clock</th>
|
|
<th class="label">Relation</th>
|
|
<th class="label">Clock Skew</th>
|
|
<th class="label">Data Delay</th>
|
|
</tr>
|
|
<tr>
|
|
<td>1</td>
|
|
<td>9.949</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/AD[8]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>27.057</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2</td>
|
|
<td>10.031</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/AD[13]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>26.974</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3</td>
|
|
<td>10.051</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/AD[10]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>26.955</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4</td>
|
|
<td>10.132</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/AD[5]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>26.873</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5</td>
|
|
<td>10.384</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/AD[6]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>26.622</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6</td>
|
|
<td>10.403</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/AD[12]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>26.602</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7</td>
|
|
<td>10.518</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/AD[11]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>26.487</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8</td>
|
|
<td>10.518</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/AD[7]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>26.487</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9</td>
|
|
<td>10.539</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/AD[9]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>26.467</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10</td>
|
|
<td>11.010</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>sequencer_inst/pc_4_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>25.995</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11</td>
|
|
<td>11.177</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>sequencer_inst/pc_3_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>25.828</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12</td>
|
|
<td>11.252</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>sequencer_inst/pc_8_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>25.753</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13</td>
|
|
<td>11.305</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>sequencer_inst/pc_6_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>25.700</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14</td>
|
|
<td>11.343</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>sequencer_inst/pc_2_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>25.662</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15</td>
|
|
<td>11.404</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>sequencer_inst/pc_7_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>25.601</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16</td>
|
|
<td>11.416</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>sequencer_inst/pc_0_s2/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>25.589</td>
|
|
</tr>
|
|
<tr>
|
|
<td>17</td>
|
|
<td>11.503</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>sequencer_inst/pc_1_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>25.502</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18</td>
|
|
<td>11.603</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>sequencer_inst/pc_5_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>25.402</td>
|
|
</tr>
|
|
<tr>
|
|
<td>19</td>
|
|
<td>16.152</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>register_file_inst/data_registers[0]_10_s1/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>20.853</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20</td>
|
|
<td>16.196</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>register_file_inst/data_registers[1]_10_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>20.809</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21</td>
|
|
<td>16.345</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>register_file_inst/data_registers[2]_10_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>20.660</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22</td>
|
|
<td>16.761</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>register_file_inst/data_registers[0]_24_s1/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>20.244</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23</td>
|
|
<td>16.852</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>register_file_inst/data_registers[2]_24_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>20.153</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24</td>
|
|
<td>16.921</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>register_file_inst/data_registers[2]_7_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>20.084</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25</td>
|
|
<td>16.921</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
<td>register_file_inst/data_registers[1]_7_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>20.084</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
|
|
<h4>Report Command:report_timing -hold -from_clock [get_clocks {i_clk}] -to_clock [get_clocks {i_clk}] -max_paths 25 -max_common_paths 1</h4>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">Path Number</th>
|
|
<th class="label">Path Slack</th>
|
|
<th class="label">From Node</th>
|
|
<th class="label">To Node</th>
|
|
<th class="label">From Clock</th>
|
|
<th class="label">To Clock</th>
|
|
<th class="label">Relation</th>
|
|
<th class="label">Clock Skew</th>
|
|
<th class="label">Data Delay</th>
|
|
</tr>
|
|
<tr>
|
|
<td>1</td>
|
|
<td>0.327</td>
|
|
<td>register_file_inst/data_registers[0]_1_s1/Q</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s/DI[1]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.576</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2</td>
|
|
<td>0.341</td>
|
|
<td>register_file_inst/data_registers[0]_0_s1/Q</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s/DI[0]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.590</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3</td>
|
|
<td>0.427</td>
|
|
<td>sequencer_inst/pc_1_s0/Q</td>
|
|
<td>sequencer_inst/pc_1_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.438</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4</td>
|
|
<td>0.427</td>
|
|
<td>sequencer_inst/pc_6_s0/Q</td>
|
|
<td>sequencer_inst/pc_6_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.438</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5</td>
|
|
<td>0.428</td>
|
|
<td>sequencer_inst/pc_7_s0/Q</td>
|
|
<td>sequencer_inst/pc_7_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.439</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6</td>
|
|
<td>0.429</td>
|
|
<td>sequencer_inst/pc_3_s0/Q</td>
|
|
<td>sequencer_inst/pc_3_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.440</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7</td>
|
|
<td>0.485</td>
|
|
<td>sequencer_inst/pc_0_s2/Q</td>
|
|
<td>sequencer_inst/pc_0_s2/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.496</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8</td>
|
|
<td>0.485</td>
|
|
<td>sequencer_inst/pc_2_s0/Q</td>
|
|
<td>sequencer_inst/pc_2_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.496</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9</td>
|
|
<td>0.514</td>
|
|
<td>register_file_inst/data_registers[0]_7_s1/Q</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_1_s/DI[3]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.763</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10</td>
|
|
<td>0.542</td>
|
|
<td>sequencer_inst/pc_4_s0/Q</td>
|
|
<td>sequencer_inst/pc_4_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.553</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11</td>
|
|
<td>0.546</td>
|
|
<td>sequencer_inst/pc_8_s0/Q</td>
|
|
<td>sequencer_inst/pc_8_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.557</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12</td>
|
|
<td>0.558</td>
|
|
<td>register_file_inst/data_registers[0]_2_s1/Q</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s/DI[2]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.807</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13</td>
|
|
<td>0.560</td>
|
|
<td>sequencer_inst/pc_5_s0/Q</td>
|
|
<td>sequencer_inst/pc_5_s0/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.571</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14</td>
|
|
<td>0.571</td>
|
|
<td>register_file_inst/data_registers[0]_2_s1/Q</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s/DI[2]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.820</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15</td>
|
|
<td>0.612</td>
|
|
<td>register_file_inst/data_registers[0]_3_s1/Q</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s/DI[3]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.861</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16</td>
|
|
<td>0.651</td>
|
|
<td>register_file_inst/data_registers[0]_4_s1/Q</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_1_s/DI[0]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.900</td>
|
|
</tr>
|
|
<tr>
|
|
<td>17</td>
|
|
<td>0.721</td>
|
|
<td>register_file_inst/data_registers[0]_8_s1/Q</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s/DI[0]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.970</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18</td>
|
|
<td>0.837</td>
|
|
<td>register_file_inst/data_registers[0]_1_s1/Q</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s/DI[1]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>1.086</td>
|
|
</tr>
|
|
<tr>
|
|
<td>19</td>
|
|
<td>0.846</td>
|
|
<td>register_file_inst/data_registers[0]_1_s1/Q</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_0_s/DI[1]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>1.095</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20</td>
|
|
<td>0.848</td>
|
|
<td>register_file_inst/data_registers[0]_16_s1/Q</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_0_s/DI[0]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>1.097</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21</td>
|
|
<td>0.851</td>
|
|
<td>register_file_inst/data_registers[0]_20_s1/Q</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_1_s/DI[0]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>1.100</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22</td>
|
|
<td>0.863</td>
|
|
<td>register_file_inst/data_registers[0]_2_s1/Q</td>
|
|
<td>sram_srom_inst/sram3_sram3_0_0_s/DI[2]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>1.112</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23</td>
|
|
<td>0.890</td>
|
|
<td>register_file_inst/data_registers[0]_19_s1/Q</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_0_s/DI[3]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>1.139</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24</td>
|
|
<td>0.891</td>
|
|
<td>sram_srom_inst/mdata_6_s0/Q</td>
|
|
<td>register_file_inst/data_registers[0]_6_s1/D</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.902</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25</td>
|
|
<td>0.896</td>
|
|
<td>register_file_inst/data_registers[0]_11_s1/Q</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s/DI[3]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>i_clk:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>1.145</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
|
|
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>Nothing to report!</h4>
|
|
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
|
|
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>Nothing to report!</h4>
|
|
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">Number</th>
|
|
<th class="label">Slack</th>
|
|
<th class="label">Actual Width</th>
|
|
<th class="label">Required Width</th>
|
|
<th class="label">Type</th>
|
|
<th class="label">Clock</th>
|
|
<th class="label">Objects</th>
|
|
</tr>
|
|
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
|
<tr>
|
|
<td>1</td>
|
|
<td>15.323</td>
|
|
<td>16.323</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>i_clk</td>
|
|
<td>strobe_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2</td>
|
|
<td>15.323</td>
|
|
<td>16.323</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>i_clk</td>
|
|
<td>o_led_5_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3</td>
|
|
<td>15.323</td>
|
|
<td>16.323</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>i_clk</td>
|
|
<td>o_led_3_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4</td>
|
|
<td>15.323</td>
|
|
<td>16.323</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>i_clk</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5</td>
|
|
<td>15.323</td>
|
|
<td>16.323</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>i_clk</td>
|
|
<td>register_file_inst/data_registers[1]_24_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6</td>
|
|
<td>15.323</td>
|
|
<td>16.323</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>i_clk</td>
|
|
<td>register_file_inst/data_registers[1]_8_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7</td>
|
|
<td>15.323</td>
|
|
<td>16.323</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>i_clk</td>
|
|
<td>register_file_inst/data_registers[2]_8_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8</td>
|
|
<td>15.323</td>
|
|
<td>16.323</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>i_clk</td>
|
|
<td>sram_srom_inst/mdata_21_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9</td>
|
|
<td>15.323</td>
|
|
<td>16.323</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>i_clk</td>
|
|
<td>sram_srom_inst/mdata_20_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10</td>
|
|
<td>15.323</td>
|
|
<td>16.323</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>i_clk</td>
|
|
<td>register_file_inst/data_registers[2]_7_s0</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
|
|
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -setup -from_clock [get_clocks {i_clk}] -to_clock [get_clocks {i_clk}] -max_paths 25 -max_common_paths 1</h4>
|
|
<h3>Path1</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>9.949</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>32.386</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.335</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.766</td>
|
|
<td>0.617</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C26[3][B]</td>
|
|
<td>sequencer_inst/seq_y_3_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.321</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C26[3][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/seq_y_3_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>32.386</td>
|
|
<td>1.065</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/AD[8]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.335</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.909, 44.015%; route: 12.888, 47.632%; tC2Q: 2.260, 8.353%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path2</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>10.031</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>32.304</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.335</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.620</td>
|
|
<td>0.470</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C27[0][A]</td>
|
|
<td>sequencer_inst/seq_y_8_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.073</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C27[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/seq_y_8_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>32.304</td>
|
|
<td>1.231</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/AD[13]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.335</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.807, 43.771%; route: 12.907, 47.851%; tC2Q: 2.260, 8.378%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path3</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>10.051</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>32.284</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.335</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.766</td>
|
|
<td>0.617</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C26[3][A]</td>
|
|
<td>sequencer_inst/seq_y_5_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.219</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C26[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/seq_y_5_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>32.284</td>
|
|
<td>1.065</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/AD[10]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.335</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.807, 43.803%; route: 12.888, 47.812%; tC2Q: 2.260, 8.384%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path4</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>10.132</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>32.203</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.335</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.369</td>
|
|
<td>0.220</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C28[0][B]</td>
|
|
<td>sequencer_inst/seq_y_0_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.822</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C28[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/seq_y_0_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>32.203</td>
|
|
<td>1.381</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/AD[5]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.335</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.807, 43.936%; route: 12.806, 47.655%; tC2Q: 2.260, 8.410%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path5</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>10.384</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>31.951</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.335</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.369</td>
|
|
<td>0.220</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C28[2][B]</td>
|
|
<td>sequencer_inst/seq_y_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.886</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C28[2][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/seq_y_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.951</td>
|
|
<td>1.065</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/AD[6]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.335</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.871, 44.592%; route: 12.491, 46.919%; tC2Q: 2.260, 8.489%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path6</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>10.403</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>31.932</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.335</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[0][B]</td>
|
|
<td>sequencer_inst/n28_s2/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.159</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R34C28[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n28_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.161</td>
|
|
<td>0.003</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C28[2][B]</td>
|
|
<td>sequencer_inst/seq_y_7_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.716</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R34C28[2][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/seq_y_7_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.932</td>
|
|
<td>1.215</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/AD[12]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.335</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.918, 44.800%; route: 12.424, 46.704%; tC2Q: 2.260, 8.495%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path7</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>10.518</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>31.816</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.335</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.176</td>
|
|
<td>0.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[1][B]</td>
|
|
<td>sequencer_inst/seq_y_6_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.629</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/seq_y_6_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.816</td>
|
|
<td>1.187</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/AD[11]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.335</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.807, 44.577%; route: 12.420, 46.891%; tC2Q: 2.260, 8.533%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path8</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>10.518</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>31.816</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.335</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.176</td>
|
|
<td>0.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[2][A]</td>
|
|
<td>sequencer_inst/seq_y_2_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.629</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/seq_y_2_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.816</td>
|
|
<td>1.187</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/AD[7]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.335</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.807, 44.577%; route: 12.420, 46.891%; tC2Q: 2.260, 8.533%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path9</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>10.539</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>31.796</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.335</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.360</td>
|
|
<td>0.210</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C27[2][B]</td>
|
|
<td>sequencer_inst/seq_y_4_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.731</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C27[2][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/seq_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.796</td>
|
|
<td>1.065</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/AD[9]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.335</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.725, 44.301%; route: 12.482, 47.160%; tC2Q: 2.260, 8.539%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path10</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>11.010</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>31.325</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.863</td>
|
|
<td>0.713</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C26[1][B]</td>
|
|
<td>sequencer_inst/n31_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.325</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R33C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n31_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.325</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C26[1][B]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_4_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C26[1][B]</td>
|
|
<td>sequencer_inst/pc_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C26[1][B]</td>
|
|
<td>sequencer_inst/pc_4_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.816, 45.454%; route: 11.919, 45.852%; tC2Q: 2.260, 8.694%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path11</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>11.177</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>31.158</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_3_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.609</td>
|
|
<td>0.459</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C26[0][A]</td>
|
|
<td>sequencer_inst/n32_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.158</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R34C26[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n32_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.158</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C26[0][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_3_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C26[0][A]</td>
|
|
<td>sequencer_inst/pc_3_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C26[0][A]</td>
|
|
<td>sequencer_inst/pc_3_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.903, 46.085%; route: 11.665, 45.165%; tC2Q: 2.260, 8.750%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path12</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>11.252</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>31.082</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_8_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.620</td>
|
|
<td>0.470</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C27[1][B]</td>
|
|
<td>sequencer_inst/n27_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.082</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R33C27[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.082</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C27[1][B]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_8_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C27[1][B]</td>
|
|
<td>sequencer_inst/pc_8_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C27[1][B]</td>
|
|
<td>sequencer_inst/pc_8_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.816, 45.882%; route: 11.677, 45.342%; tC2Q: 2.260, 8.776%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path13</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>11.305</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>31.029</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_6_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[0][A]</td>
|
|
<td>sequencer_inst/n29_s2/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R34C28[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n29_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.567</td>
|
|
<td>0.418</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][A]</td>
|
|
<td>sequencer_inst/n29_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.029</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n29_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>31.029</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_6_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][A]</td>
|
|
<td>sequencer_inst/pc_6_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C27[1][A]</td>
|
|
<td>sequencer_inst/pc_6_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.816, 45.977%; route: 11.624, 45.229%; tC2Q: 2.260, 8.794%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path14</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>11.343</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>30.991</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_2_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.620</td>
|
|
<td>0.470</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C27[2][A]</td>
|
|
<td>sequencer_inst/n33_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.991</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C27[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n33_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.991</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C27[2][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_2_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C27[2][A]</td>
|
|
<td>sequencer_inst/pc_2_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C27[2][A]</td>
|
|
<td>sequencer_inst/pc_2_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.725, 45.691%; route: 11.677, 45.503%; tC2Q: 2.260, 8.807%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path15</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>11.404</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>30.930</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_7_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.360</td>
|
|
<td>0.210</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C27[0][A]</td>
|
|
<td>sequencer_inst/n28_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.930</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R34C27[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n28_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.930</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[0][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_7_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[0][A]</td>
|
|
<td>sequencer_inst/pc_7_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C27[0][A]</td>
|
|
<td>sequencer_inst/pc_7_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.924, 46.577%; route: 11.417, 44.596%; tC2Q: 2.260, 8.828%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path16</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>11.416</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>30.918</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_0_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.369</td>
|
|
<td>0.220</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C28[2][A]</td>
|
|
<td>sequencer_inst/n35_s8/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.918</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R33C28[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n35_s8/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.918</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C28[2][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_0_s2/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C28[2][A]</td>
|
|
<td>sequencer_inst/pc_0_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C28[2][A]</td>
|
|
<td>sequencer_inst/pc_0_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.903, 46.516%; route: 11.426, 44.652%; tC2Q: 2.260, 8.832%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path17</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>11.503</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>30.831</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_1_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.369</td>
|
|
<td>0.220</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C28[1][A]</td>
|
|
<td>sequencer_inst/n34_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.831</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R33C28[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n34_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.831</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C28[1][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_1_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C28[1][A]</td>
|
|
<td>sequencer_inst/pc_1_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C28[1][A]</td>
|
|
<td>sequencer_inst/pc_1_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.816, 46.334%; route: 11.426, 44.804%; tC2Q: 2.260, 8.862%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path18</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>11.603</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>30.731</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_5_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.258</td>
|
|
<td>0.955</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td>alu_inst/alu_y_4_s7/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.629</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s7/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.634</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td>alu_inst/alu_y_4_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.096</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C29[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.097</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td>alu_inst/alu_y_4_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.646</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.647</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td>alu_inst/alu_y_4_s0/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.100</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_4_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.522</td>
|
|
<td>1.421</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td>sequencer_inst/n27_s16/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.092</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s16/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.236</td>
|
|
<td>0.144</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td>sequencer_inst/n27_s12/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.785</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s12/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.957</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td>sequencer_inst/n27_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.328</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C25[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.012</td>
|
|
<td>0.684</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td>sequencer_inst/n27_s9/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.474</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R27C24[0][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s9/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>27.476</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td>sequencer_inst/n27_s6/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.046</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.218</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td>sequencer_inst/n27_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>28.671</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>5</td>
|
|
<td>R27C25[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>29.697</td>
|
|
<td>1.026</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td>sequencer_inst/n27_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.150</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>18</td>
|
|
<td>R34C28[3][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.360</td>
|
|
<td>0.210</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][B]</td>
|
|
<td>sequencer_inst/n30_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.731</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n30_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>30.731</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][B]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_5_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][B]</td>
|
|
<td>sequencer_inst/pc_5_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C27[1][B]</td>
|
|
<td>sequencer_inst/pc_5_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>19</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 11.725, 46.158%; route: 11.417, 44.945%; tC2Q: 2.260, 8.897%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path19</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>16.152</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>26.182</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>register_file_inst/data_registers[0]_10_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[10]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.153</td>
|
|
<td>0.850</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R26C24[2][A]</td>
|
|
<td>alu_inst/alu_y_10_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.524</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R26C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_10_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.938</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C24[3][A]</td>
|
|
<td>alu_inst/alu_y_10_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.487</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C24[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_10_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.488</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C24[3][B]</td>
|
|
<td>alu_inst/alu_y_10_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.941</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C24[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_10_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.612</td>
|
|
<td>2.671</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R20C31[1][A]</td>
|
|
<td>register_file_inst/n868_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.182</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R20C31[1][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/n868_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.182</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R20C31[1][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_10_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R20C31[1][A]</td>
|
|
<td>register_file_inst/data_registers[0]_10_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R20C31[1][A]</td>
|
|
<td>register_file_inst/data_registers[0]_10_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>11</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 8.034, 38.527%; route: 10.559, 50.635%; tC2Q: 2.260, 10.838%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path20</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>16.196</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>26.139</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>register_file_inst/data_registers[1]_10_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[10]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.153</td>
|
|
<td>0.850</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R26C24[2][A]</td>
|
|
<td>alu_inst/alu_y_10_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.524</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R26C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_10_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.938</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C24[3][A]</td>
|
|
<td>alu_inst/alu_y_10_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.487</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C24[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_10_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.488</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C24[3][B]</td>
|
|
<td>alu_inst/alu_y_10_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.941</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C24[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_10_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>26.139</td>
|
|
<td>3.198</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R21C31[2][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[1]_10_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R21C31[2][A]</td>
|
|
<td>register_file_inst/data_registers[1]_10_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R21C31[2][A]</td>
|
|
<td>register_file_inst/data_registers[1]_10_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>10</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 7.464, 35.868%; route: 11.085, 53.271%; tC2Q: 2.260, 10.860%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path21</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>16.345</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>25.989</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>register_file_inst/data_registers[2]_10_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[10]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.153</td>
|
|
<td>0.850</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R26C24[2][A]</td>
|
|
<td>alu_inst/alu_y_10_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.524</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R26C24[2][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_10_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.938</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C24[3][A]</td>
|
|
<td>alu_inst/alu_y_10_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.487</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R29C24[3][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_10_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.488</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C24[3][B]</td>
|
|
<td>alu_inst/alu_y_10_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.941</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R29C24[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_10_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.989</td>
|
|
<td>3.048</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R21C31[1][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[2]_10_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R21C31[1][A]</td>
|
|
<td>register_file_inst/data_registers[2]_10_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R21C31[1][A]</td>
|
|
<td>register_file_inst/data_registers[2]_10_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>10</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 7.464, 36.129%; route: 10.936, 52.932%; tC2Q: 2.260, 10.939%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path22</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>16.761</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>25.573</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>register_file_inst/data_registers[0]_24_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[24]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.716</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R22C24[3][B]</td>
|
|
<td>alu_inst/alu_y_24_s11/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.271</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R22C24[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_24_s11/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.927</td>
|
|
<td>0.656</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[3][B]</td>
|
|
<td>alu_inst/alu_y_24_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.298</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_24_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.954</td>
|
|
<td>0.656</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C23[1][A]</td>
|
|
<td>alu_inst/alu_y_24_s/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.509</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R31C23[1][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_24_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.111</td>
|
|
<td>1.602</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C35[0][A]</td>
|
|
<td>register_file_inst/n854_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.573</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R30C35[0][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/n854_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.573</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R30C35[0][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_24_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R30C35[0][A]</td>
|
|
<td>register_file_inst/data_registers[0]_24_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R30C35[0][A]</td>
|
|
<td>register_file_inst/data_registers[0]_24_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>11</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 8.034, 39.686%; route: 9.950, 49.150%; tC2Q: 2.260, 11.164%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path23</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>16.852</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>25.482</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>register_file_inst/data_registers[2]_24_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[24]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.716</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R22C24[3][B]</td>
|
|
<td>alu_inst/alu_y_24_s11/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.271</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R22C24[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_24_s11/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.927</td>
|
|
<td>0.656</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[3][B]</td>
|
|
<td>alu_inst/alu_y_24_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.298</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C24[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_24_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.954</td>
|
|
<td>0.656</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C23[1][A]</td>
|
|
<td>alu_inst/alu_y_24_s/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.509</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R31C23[1][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_24_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.482</td>
|
|
<td>1.973</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C35[2][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[2]_24_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R30C35[2][A]</td>
|
|
<td>register_file_inst/data_registers[2]_24_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R30C35[2][A]</td>
|
|
<td>register_file_inst/data_registers[2]_24_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>10</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 7.572, 37.573%; route: 10.321, 51.213%; tC2Q: 2.260, 11.214%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path24</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>16.921</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>25.413</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>register_file_inst/data_registers[2]_7_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[7]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.958</td>
|
|
<td>0.655</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R20C24[1][A]</td>
|
|
<td>alu_inst/alu_y_7_s8/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.411</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R20C24[1][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_7_s8/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.901</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R24C24[3][B]</td>
|
|
<td>alu_inst/alu_y_7_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.363</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R24C24[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_7_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.535</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R24C25[3][B]</td>
|
|
<td>alu_inst/alu_y_7_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.997</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R24C25[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_7_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.999</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R24C25[2][B]</td>
|
|
<td>alu_inst/alu_y_7_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.516</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R24C25[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_7_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.413</td>
|
|
<td>1.897</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C35[1][B]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[2]_7_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R30C35[1][B]</td>
|
|
<td>register_file_inst/data_registers[2]_7_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R30C35[1][B]</td>
|
|
<td>register_file_inst/data_registers[2]_7_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>11</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 7.985, 39.758%; route: 9.839, 48.989%; tC2Q: 2.260, 11.253%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path25</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>16.921</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>25.413</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>42.334</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>register_file_inst/data_registers[1]_7_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.088</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.329</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.589</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>73</td>
|
|
<td>BSRAM_R46[9]</td>
|
|
<td style=" font-weight:bold;">microcode_rom_microcode_rom_0_0_s/DO[11]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.569</td>
|
|
<td>0.980</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s44/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.086</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C37[3][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s44/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.499</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_CL_s41/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.870</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_CL_s41/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.283</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td>register_file_inst/addr_registers[0]_ER_init_s20/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.654</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R31C33[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/addr_registers[0]_ER_init_s20/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.842</td>
|
|
<td>1.188</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td>register_file_inst/alu_a_4_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.397</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C30[3][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.810</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td>register_file_inst/alu_a_4_s/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.327</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R30C33[0][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/alu_a_4_s/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16.543</td>
|
|
<td>3.216</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>72</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td>alu_inst/mult_172_s1/A[4]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.303</td>
|
|
<td>3.760</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>DSP_R19[2]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/mult_172_s1/DOUT[7]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.958</td>
|
|
<td>0.655</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R20C24[1][A]</td>
|
|
<td>alu_inst/alu_y_7_s8/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.411</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R20C24[1][A]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_7_s8/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21.901</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R24C24[3][B]</td>
|
|
<td>alu_inst/alu_y_7_s4/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.363</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R24C24[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_7_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.535</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R24C25[3][B]</td>
|
|
<td>alu_inst/alu_y_7_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.997</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R24C25[3][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_7_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22.999</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R24C25[2][B]</td>
|
|
<td>alu_inst/alu_y_7_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23.516</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>6</td>
|
|
<td>R24C25[2][B]</td>
|
|
<td style=" background: #97FFFF;">alu_inst/alu_y_7_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25.413</td>
|
|
<td>1.897</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C35[1][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[1]_7_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>37.040</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>39.128</td>
|
|
<td>2.088</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.369</td>
|
|
<td>3.241</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C35[1][A]</td>
|
|
<td>register_file_inst/data_registers[1]_7_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>42.334</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R31C35[1][A]</td>
|
|
<td>register_file_inst/data_registers[1]_7_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>37.040</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>11</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 7.985, 39.758%; route: 9.839, 48.989%; tC2Q: 2.260, 11.253%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 2.088, 39.180%; route: 3.241, 60.820%</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -hold -from_clock [get_clocks {i_clk}] -to_clock [get_clocks {i_clk}] -max_paths 25 -max_common_paths 1</h4>
|
|
<h3>Path1</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.327</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.159</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_1_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R24C31[0][A]</td>
|
|
<td>register_file_inst/data_registers[0]_1_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>6</td>
|
|
<td>R24C31[0][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_1_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.159</td>
|
|
<td>0.374</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[8]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram0_sram0_0_0_s/DI[1]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[8]</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[8]</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.374, 64.958%; tC2Q: 0.202, 35.042%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path2</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.341</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.173</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_0_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C32[1][A]</td>
|
|
<td>register_file_inst/data_registers[0]_0_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>6</td>
|
|
<td>R23C32[1][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_0_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.173</td>
|
|
<td>0.388</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[8]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram0_sram0_0_0_s/DI[0]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[8]</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[8]</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.388, 65.750%; tC2Q: 0.202, 34.250%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path3</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.427</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.021</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.594</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>sequencer_inst/pc_1_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_1_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C28[1][A]</td>
|
|
<td>sequencer_inst/pc_1_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>6</td>
|
|
<td>R33C28[1][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_1_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.789</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C28[1][A]</td>
|
|
<td>sequencer_inst/n34_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.021</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R33C28[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n34_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.021</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C28[1][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_1_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C28[1][A]</td>
|
|
<td>sequencer_inst/pc_1_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.594</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C28[1][A]</td>
|
|
<td>sequencer_inst/pc_1_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path4</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.427</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.021</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.594</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>sequencer_inst/pc_6_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_6_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][A]</td>
|
|
<td>sequencer_inst/pc_6_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>4</td>
|
|
<td>R34C27[1][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_6_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.789</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][A]</td>
|
|
<td>sequencer_inst/n29_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.021</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n29_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.021</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_6_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][A]</td>
|
|
<td>sequencer_inst/pc_6_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.594</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C27[1][A]</td>
|
|
<td>sequencer_inst/pc_6_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path5</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.428</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.022</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.594</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>sequencer_inst/pc_7_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_7_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[0][A]</td>
|
|
<td>sequencer_inst/pc_7_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>4</td>
|
|
<td>R34C27[0][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_7_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.790</td>
|
|
<td>0.005</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[0][A]</td>
|
|
<td>sequencer_inst/n28_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.022</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R34C27[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n28_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.022</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C27[0][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_7_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[0][A]</td>
|
|
<td>sequencer_inst/pc_7_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.594</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C27[0][A]</td>
|
|
<td>sequencer_inst/pc_7_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path6</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.429</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.023</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.594</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>sequencer_inst/pc_3_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_3_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C26[0][A]</td>
|
|
<td>sequencer_inst/pc_3_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>6</td>
|
|
<td>R34C26[0][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_3_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.791</td>
|
|
<td>0.006</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C26[0][A]</td>
|
|
<td>sequencer_inst/n32_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.023</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R34C26[0][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n32_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.023</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C26[0][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_3_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C26[0][A]</td>
|
|
<td>sequencer_inst/pc_3_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.594</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C26[0][A]</td>
|
|
<td>sequencer_inst/pc_3_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path7</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.485</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.079</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.594</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>sequencer_inst/pc_0_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_0_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C28[2][A]</td>
|
|
<td>sequencer_inst/pc_0_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R33C28[2][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_0_s2/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.789</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C28[2][A]</td>
|
|
<td>sequencer_inst/n35_s8/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.079</td>
|
|
<td>0.290</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R33C28[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n35_s8/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.079</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C28[2][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_0_s2/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C28[2][A]</td>
|
|
<td>sequencer_inst/pc_0_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.594</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C28[2][A]</td>
|
|
<td>sequencer_inst/pc_0_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.290, 58.507%; route: 0.004, 0.740%; tC2Q: 0.202, 40.753%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path8</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.485</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.079</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.594</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>sequencer_inst/pc_2_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_2_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C27[2][A]</td>
|
|
<td>sequencer_inst/pc_2_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>4</td>
|
|
<td>R33C27[2][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_2_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.789</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C27[2][A]</td>
|
|
<td>sequencer_inst/n33_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.079</td>
|
|
<td>0.290</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R33C27[2][A]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n33_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.079</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C27[2][A]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_2_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C27[2][A]</td>
|
|
<td>sequencer_inst/pc_2_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.594</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C27[2][A]</td>
|
|
<td>sequencer_inst/pc_2_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.290, 58.507%; route: 0.004, 0.740%; tC2Q: 0.202, 40.753%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path9</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.514</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.346</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_7_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_1_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R25C34[0][A]</td>
|
|
<td>register_file_inst/data_registers[0]_7_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>21</td>
|
|
<td>R25C34[0][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_7_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.346</td>
|
|
<td>0.561</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[10]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram0_sram0_0_1_s/DI[3]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[10]</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_1_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[10]</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_1_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.561, 73.535%; tC2Q: 0.202, 26.465%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path10</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.542</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.136</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.594</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>sequencer_inst/pc_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C26[1][B]</td>
|
|
<td>sequencer_inst/pc_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.784</td>
|
|
<td>0.201</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>4</td>
|
|
<td>R33C26[1][B]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.904</td>
|
|
<td>0.120</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C26[1][B]</td>
|
|
<td>sequencer_inst/n31_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.136</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C26[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n31_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.136</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C26[1][B]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_4_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C26[1][B]</td>
|
|
<td>sequencer_inst/pc_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.594</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C26[1][B]</td>
|
|
<td>sequencer_inst/pc_4_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path11</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.546</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.140</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.594</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>sequencer_inst/pc_8_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_8_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C27[1][B]</td>
|
|
<td>sequencer_inst/pc_8_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.784</td>
|
|
<td>0.201</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R33C27[1][B]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_8_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.908</td>
|
|
<td>0.124</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C27[1][B]</td>
|
|
<td>sequencer_inst/n27_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.140</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C27[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n27_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.140</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C27[1][B]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_8_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C27[1][B]</td>
|
|
<td>sequencer_inst/pc_8_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.594</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C27[1][B]</td>
|
|
<td>sequencer_inst/pc_8_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path12</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.558</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.390</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_2_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C35[0][B]</td>
|
|
<td>register_file_inst/data_registers[0]_2_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>21</td>
|
|
<td>R31C35[0][B]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_2_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.036</td>
|
|
<td>0.251</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C35[2][A]</td>
|
|
<td>sram_srom_inst/wdata1_2_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.268</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R27C35[2][A]</td>
|
|
<td style=" background: #97FFFF;">sram_srom_inst/wdata1_2_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.390</td>
|
|
<td>0.122</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[9]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram1_sram1_0_0_s/DI[2]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[9]</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[9]</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 28.736%; route: 0.373, 46.244%; tC2Q: 0.202, 25.020%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path13</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.560</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.154</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.594</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>sequencer_inst/pc_5_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sequencer_inst/pc_5_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][B]</td>
|
|
<td>sequencer_inst/pc_5_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>6</td>
|
|
<td>R34C27[1][B]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_5_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.790</td>
|
|
<td>0.005</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][B]</td>
|
|
<td>sequencer_inst/n30_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.154</td>
|
|
<td>0.364</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][B]</td>
|
|
<td style=" background: #97FFFF;">sequencer_inst/n30_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.154</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][B]</td>
|
|
<td style=" font-weight:bold;">sequencer_inst/pc_5_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C27[1][B]</td>
|
|
<td>sequencer_inst/pc_5_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.594</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C27[1][B]</td>
|
|
<td>sequencer_inst/pc_5_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.364, 63.760%; route: 0.005, 0.856%; tC2Q: 0.202, 35.383%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path14</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.571</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.403</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_2_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C35[0][B]</td>
|
|
<td>register_file_inst/data_registers[0]_2_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>21</td>
|
|
<td>R31C35[0][B]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_2_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.403</td>
|
|
<td>0.618</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[8]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram0_sram0_0_0_s/DI[2]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[8]</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[8]</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.618, 75.372%; tC2Q: 0.202, 24.628%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path15</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.612</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.444</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_3_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R21C33[0][B]</td>
|
|
<td>register_file_inst/data_registers[0]_3_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>19</td>
|
|
<td>R21C33[0][B]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_3_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.444</td>
|
|
<td>0.659</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[8]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram0_sram0_0_0_s/DI[3]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[8]</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[8]</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.659, 76.536%; tC2Q: 0.202, 23.464%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path16</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.651</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.483</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_4_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_1_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R26C30[2][A]</td>
|
|
<td>register_file_inst/data_registers[0]_4_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>23</td>
|
|
<td>R26C30[2][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_4_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.483</td>
|
|
<td>0.698</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[10]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram0_sram0_0_1_s/DI[0]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[10]</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_1_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[10]</td>
|
|
<td>sram_srom_inst/sram0_sram0_0_1_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.698, 77.560%; tC2Q: 0.202, 22.440%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path17</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.721</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.553</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_8_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R22C35[1][B]</td>
|
|
<td>register_file_inst/data_registers[0]_8_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>4</td>
|
|
<td>R22C35[1][B]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_8_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.199</td>
|
|
<td>0.414</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C35[1][B]</td>
|
|
<td>sram_srom_inst/wdata1_0_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.431</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R29C35[1][B]</td>
|
|
<td style=" background: #97FFFF;">sram_srom_inst/wdata1_0_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.553</td>
|
|
<td>0.122</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[9]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram1_sram1_0_0_s/DI[0]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[9]</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[9]</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 23.919%; route: 0.536, 55.255%; tC2Q: 0.202, 20.826%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path18</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.837</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.669</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_1_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R24C31[0][A]</td>
|
|
<td>register_file_inst/data_registers[0]_1_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>6</td>
|
|
<td>R24C31[0][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_1_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.059</td>
|
|
<td>0.274</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R26C35[2][A]</td>
|
|
<td>sram_srom_inst/wdata1_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.403</td>
|
|
<td>0.344</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R26C35[2][A]</td>
|
|
<td style=" background: #97FFFF;">sram_srom_inst/wdata1_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.669</td>
|
|
<td>0.266</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[9]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram1_sram1_0_0_s/DI[1]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[9]</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[9]</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.344, 31.680%; route: 0.540, 49.717%; tC2Q: 0.202, 18.603%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path19</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.846</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.678</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_1_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R24C31[0][A]</td>
|
|
<td>register_file_inst/data_registers[0]_1_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>6</td>
|
|
<td>R24C31[0][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_1_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.320</td>
|
|
<td>0.535</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C38[0][A]</td>
|
|
<td>sram_srom_inst/wdata2_1_s1/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.555</td>
|
|
<td>0.235</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">sram_srom_inst/wdata2_1_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.678</td>
|
|
<td>0.123</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[10]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram2_sram2_0_0_s/DI[1]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[10]</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[10]</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.235, 21.454%; route: 0.658, 60.105%; tC2Q: 0.202, 18.441%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path20</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.848</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.680</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_16_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R25C33[2][A]</td>
|
|
<td>register_file_inst/data_registers[0]_16_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>3</td>
|
|
<td>R25C33[2][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_16_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.196</td>
|
|
<td>0.411</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R26C38[3][A]</td>
|
|
<td>sram_srom_inst/wdata2_0_s1/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.431</td>
|
|
<td>0.235</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R26C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">sram_srom_inst/wdata2_0_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.680</td>
|
|
<td>0.249</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[10]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram2_sram2_0_0_s/DI[0]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[10]</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[10]</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.235, 21.420%; route: 0.660, 60.168%; tC2Q: 0.202, 18.412%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path21</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.851</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.683</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_20_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_1_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C36[1][B]</td>
|
|
<td>register_file_inst/data_registers[0]_20_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>3</td>
|
|
<td>R27C36[1][B]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_20_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.909</td>
|
|
<td>0.124</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C38[1][B]</td>
|
|
<td>sram_srom_inst/wdata2_4_s1/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.300</td>
|
|
<td>0.391</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">sram_srom_inst/wdata2_4_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.683</td>
|
|
<td>0.382</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[11]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram2_sram2_0_1_s/DI[0]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[11]</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_1_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[11]</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_1_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.391, 35.549%; route: 0.507, 46.085%; tC2Q: 0.202, 18.366%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path22</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.863</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.695</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_2_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram3_sram3_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C35[0][B]</td>
|
|
<td>register_file_inst/data_registers[0]_2_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>21</td>
|
|
<td>R31C35[0][B]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_2_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.036</td>
|
|
<td>0.251</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C35[3][A]</td>
|
|
<td>sram_srom_inst/wdata3_2_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.268</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R27C35[3][A]</td>
|
|
<td style=" background: #97FFFF;">sram_srom_inst/wdata3_2_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.695</td>
|
|
<td>0.427</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[12]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram3_sram3_0_0_s/DI[2]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[12]</td>
|
|
<td>sram_srom_inst/sram3_sram3_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[12]</td>
|
|
<td>sram_srom_inst/sram3_sram3_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 20.855%; route: 0.678, 60.987%; tC2Q: 0.202, 18.158%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path23</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.890</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.722</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_19_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R21C34[0][A]</td>
|
|
<td>register_file_inst/data_registers[0]_19_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>3</td>
|
|
<td>R21C34[0][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_19_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.208</td>
|
|
<td>0.423</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C38[1][A]</td>
|
|
<td>sram_srom_inst/wdata2_3_s1/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.599</td>
|
|
<td>0.391</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">sram_srom_inst/wdata2_3_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.722</td>
|
|
<td>0.123</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[10]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram2_sram2_0_0_s/DI[3]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[10]</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[10]</td>
|
|
<td>sram_srom_inst/sram2_sram2_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.391, 34.322%; route: 0.546, 47.947%; tC2Q: 0.202, 17.731%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path24</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.485</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.594</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>sram_srom_inst/mdata_6_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>register_file_inst/data_registers[0]_6_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R30C36[0][A]</td>
|
|
<td>sram_srom_inst/mdata_6_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.784</td>
|
|
<td>0.201</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R30C36[0][A]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/mdata_6_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.906</td>
|
|
<td>0.122</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[2][B]</td>
|
|
<td>register_file_inst/n872_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.138</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[2][B]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/n872_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.141</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[1][A]</td>
|
|
<td>register_file_inst/n872_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.485</td>
|
|
<td>0.344</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[1][A]</td>
|
|
<td style=" background: #97FFFF;">register_file_inst/n872_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.485</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C36[1][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_6_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C36[1][A]</td>
|
|
<td>register_file_inst/data_registers[0]_6_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.594</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R31C36[1][A]</td>
|
|
<td>register_file_inst/data_registers[0]_6_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>3</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.576, 63.830%; route: 0.125, 13.896%; tC2Q: 0.201, 22.274%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path25</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.896</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.728</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>3.832</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>register_file_inst/data_registers[0]_11_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>i_clk:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R22C35[1][A]</td>
|
|
<td>register_file_inst/data_registers[0]_11_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.785</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>4</td>
|
|
<td>R22C35[1][A]</td>
|
|
<td style=" font-weight:bold;">register_file_inst/data_registers[0]_11_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.172</td>
|
|
<td>0.387</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C35[0][B]</td>
|
|
<td>sram_srom_inst/wdata1_3_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.462</td>
|
|
<td>0.290</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R27C35[0][B]</td>
|
|
<td style=" background: #97FFFF;">sram_srom_inst/wdata1_3_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.728</td>
|
|
<td>0.266</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[9]</td>
|
|
<td style=" font-weight:bold;">sram_srom_inst/sram1_sram1_0_0_s/DI[3]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.392</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>163</td>
|
|
<td>IOL7[A]</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.583</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[9]</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.832</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[9]</td>
|
|
<td>sram_srom_inst/sram1_sram1_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.290, 25.333%; route: 0.653, 57.022%; tC2Q: 0.202, 17.645%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 1.392, 38.851%; route: 2.191, 61.149%</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>No recovery paths to report!</h4>
|
|
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>No removal paths to report!</h4>
|
|
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
|
|
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
|
<h3>MPW1</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>15.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>16.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Objects:</td>
|
|
<td>strobe_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.832</td>
|
|
<td>2.314</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.300</td>
|
|
<td>3.468</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>strobe_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>38.432</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>40.623</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>strobe_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW2</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>15.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>16.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Objects:</td>
|
|
<td>o_led_5_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.832</td>
|
|
<td>2.314</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.300</td>
|
|
<td>3.468</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>o_led_5_s2/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>38.432</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>40.623</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>o_led_5_s2/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW3</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>15.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>16.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Objects:</td>
|
|
<td>o_led_3_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.832</td>
|
|
<td>2.314</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.300</td>
|
|
<td>3.468</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>o_led_3_s1/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>38.432</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>40.623</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>o_led_3_s1/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW4</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>15.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>16.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Objects:</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.832</td>
|
|
<td>2.314</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.300</td>
|
|
<td>3.468</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>38.432</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>40.623</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>microcode_rom_microcode_rom_0_0_s/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW5</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>15.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>16.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Objects:</td>
|
|
<td>register_file_inst/data_registers[1]_24_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.832</td>
|
|
<td>2.314</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.300</td>
|
|
<td>3.468</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>register_file_inst/data_registers[1]_24_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>38.432</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>40.623</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>register_file_inst/data_registers[1]_24_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW6</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>15.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>16.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Objects:</td>
|
|
<td>register_file_inst/data_registers[1]_8_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.832</td>
|
|
<td>2.314</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.300</td>
|
|
<td>3.468</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>register_file_inst/data_registers[1]_8_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>38.432</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>40.623</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>register_file_inst/data_registers[1]_8_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW7</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>15.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>16.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Objects:</td>
|
|
<td>register_file_inst/data_registers[2]_8_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.832</td>
|
|
<td>2.314</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.300</td>
|
|
<td>3.468</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>register_file_inst/data_registers[2]_8_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>38.432</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>40.623</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>register_file_inst/data_registers[2]_8_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW8</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>15.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>16.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Objects:</td>
|
|
<td>sram_srom_inst/mdata_21_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.832</td>
|
|
<td>2.314</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.300</td>
|
|
<td>3.468</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>sram_srom_inst/mdata_21_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>38.432</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>40.623</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>sram_srom_inst/mdata_21_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW9</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>15.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>16.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Objects:</td>
|
|
<td>sram_srom_inst/mdata_20_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.832</td>
|
|
<td>2.314</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.300</td>
|
|
<td>3.468</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>sram_srom_inst/mdata_20_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>38.432</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>40.623</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>sram_srom_inst/mdata_20_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW10</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>15.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>16.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Objects:</td>
|
|
<td>register_file_inst/data_registers[2]_7_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18.518</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20.832</td>
|
|
<td>2.314</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24.300</td>
|
|
<td>3.468</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>register_file_inst/data_registers[2]_7_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>i_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td>37.040</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>38.432</td>
|
|
<td>1.392</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>i_clk_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>40.623</td>
|
|
<td>2.191</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>register_file_inst/data_registers[2]_7_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
|
|
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">NET NAME</th>
|
|
<th class="label">WORST SLACK</th>
|
|
<th class="label">MAX DELAY</th>
|
|
</tr>
|
|
<tr>
|
|
<td>163</td>
|
|
<td>i_clk_d</td>
|
|
<td>9.949</td>
|
|
<td>3.468</td>
|
|
</tr>
|
|
<tr>
|
|
<td>122</td>
|
|
<td>alu_op[0]_1_2</td>
|
|
<td>15.234</td>
|
|
<td>1.669</td>
|
|
</tr>
|
|
<tr>
|
|
<td>92</td>
|
|
<td>alu_inst/o_y_0_37</td>
|
|
<td>14.591</td>
|
|
<td>2.429</td>
|
|
</tr>
|
|
<tr>
|
|
<td>87</td>
|
|
<td>rf_rs2_data[3]</td>
|
|
<td>14.423</td>
|
|
<td>2.029</td>
|
|
</tr>
|
|
<tr>
|
|
<td>73</td>
|
|
<td>uinst[12]</td>
|
|
<td>9.949</td>
|
|
<td>1.174</td>
|
|
</tr>
|
|
<tr>
|
|
<td>71</td>
|
|
<td>rf_rs2_data[1]</td>
|
|
<td>13.755</td>
|
|
<td>1.931</td>
|
|
</tr>
|
|
<tr>
|
|
<td>69</td>
|
|
<td>rf_rs2_data[0]</td>
|
|
<td>14.274</td>
|
|
<td>2.505</td>
|
|
</tr>
|
|
<tr>
|
|
<td>61</td>
|
|
<td>uinst[10]</td>
|
|
<td>13.046</td>
|
|
<td>2.250</td>
|
|
</tr>
|
|
<tr>
|
|
<td>57</td>
|
|
<td>uinst[13]</td>
|
|
<td>10.193</td>
|
|
<td>2.087</td>
|
|
</tr>
|
|
<tr>
|
|
<td>54</td>
|
|
<td>alu_op[3]</td>
|
|
<td>15.365</td>
|
|
<td>2.518</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
|
|
<h4>Report Command:report_route_congestion -max_grids 10</h4>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">GRID LOC</th>
|
|
<th class="label">ROUTE CONGESTIONS</th>
|
|
</tr>
|
|
<tr>
|
|
<td>R2C2</td>
|
|
<td>100.00%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R2C4</td>
|
|
<td>100.00%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R2C8</td>
|
|
<td>100.00%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R2C16</td>
|
|
<td>100.00%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R2C32</td>
|
|
<td>100.00%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R3C10</td>
|
|
<td>100.00%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R4C20</td>
|
|
<td>100.00%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R6C40</td>
|
|
<td>100.00%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R12C15</td>
|
|
<td>100.00%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R22C20</td>
|
|
<td>100.00%</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
|
|
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">SDC Command Type</th>
|
|
<th class="label">State</th>
|
|
<th class="label">Detail Command</th>
|
|
</tr>
|
|
<tr>
|
|
<td>TC_CLOCK</td>
|
|
<td>Actived</td>
|
|
<td>create_clock -name i_clk -period 37.04 -waveform {0 18.518} [get_ports {i_clk}] -add</td>
|
|
</tr>
|
|
<tr>
|
|
<td>TC_REPORT_TIMING</td>
|
|
<td>Actived</td>
|
|
<td>report_timing -hold -from_clock [get_clocks {i_clk}] -to_clock [get_clocks {i_clk}] -max_paths 25 -max_common_paths 1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>TC_REPORT_TIMING</td>
|
|
<td>Actived</td>
|
|
<td>report_timing -setup -from_clock [get_clocks {i_clk}] -to_clock [get_clocks {i_clk}] -max_paths 25 -max_common_paths 1</td>
|
|
</tr>
|
|
</table>
|
|
</div><!-- content -->
|
|
</body>
|
|
</html>
|