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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Pin Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Pin Messages</a></li>
<!--<li><a href="#Summary" style=" font-size: 16px;">Pin Summaries</a></li>-->
<li><a href="#Pin_Details" style=" font-size: 16px;">Pin Details</a>
<ul>
<li><a href="#Pinout_by_Port_Name" style=" font-size: 14px;">Pinout by Port Name</a></li>
<li><a href="#All_Package_Pins" style=" font-size: 14px;">All Package Pins</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="Message">Pin Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Pin Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>/Users/car/Projects/hope/hope/impl/gwsynthesis/hope.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>/Users/car/Projects/hope/tangnano20k.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>/Users/car/Projects/hope/tangnano20k.sdc</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.11.03 Education</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2AR-LV18QN88C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2AR-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Fri Feb 20 01:45:30 2026
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Pin_Details">Pin Details</a></h1>
<h2><a name="Pinout_by_Port_Name">Pinout by Port Name:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Port Name</b></td>
<td><b>Diff Pair</b></td>
<td><b>Loc./Bank</b></td>
<td><b>Constraint</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>CFG</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Vref</b></td>
<td><b>Single Resistor</b></td>
<td><b>Diff Resistor</b></td>
<td><b>BankVccio</b></td>
</tr>
<tr>
<td class="label">i_clk</td>
<td>-</td>
<td>4/7</td>
<td>Y</td>
<td>in</td>
<td>IOL7[A]</td>
<td>LPLL1_T_in</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i_rst_n</td>
<td>-</td>
<td>88/3</td>
<td>Y</td>
<td>in</td>
<td>IOR30[A]</td>
<td>MODE0</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">i_uart_rx</td>
<td>-</td>
<td>70/1</td>
<td>Y</td>
<td>in</td>
<td>IOT44[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">o_uart_tx</td>
<td>-</td>
<td>69/1</td>
<td>Y</td>
<td>out</td>
<td>IOT50[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">o_led[0]</td>
<td>-</td>
<td>15/6</td>
<td>Y</td>
<td>out</td>
<td>IOL47[A]</td>
<td>LPLL2_T_fb</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">o_led[1]</td>
<td>-</td>
<td>16/6</td>
<td>Y</td>
<td>out</td>
<td>IOL47[B]</td>
<td>LPLL2_C_fb</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">o_led[2]</td>
<td>-</td>
<td>17/6</td>
<td>Y</td>
<td>out</td>
<td>IOL49[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">o_led[3]</td>
<td>-</td>
<td>18/6</td>
<td>Y</td>
<td>out</td>
<td>IOL49[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">o_led[4]</td>
<td>-</td>
<td>19/6</td>
<td>Y</td>
<td>out</td>
<td>IOL51[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">o_led[5]</td>
<td>-</td>
<td>20/6</td>
<td>Y</td>
<td>out</td>
<td>IOL51[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
</table>
<br/>
<h2><a name="All_Package_Pins">All Package Pins:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Loc./Bank</b></td>
<td><b>Signal</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>CFG</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Vref</b></td>
<td><b>Single Resistor</b></td>
<td><b>Diff Resistor</b></td>
<td><b>Bank Vccio</b></td>
</tr>
<tr>
<td class="label">86/0</td>
<td>-</td>
<td>in</td>
<td>IOT4[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">85/0</td>
<td>-</td>
<td>in</td>
<td>IOT4[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">84/0</td>
<td>-</td>
<td>in</td>
<td>IOT6[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">83/0</td>
<td>-</td>
<td>in</td>
<td>IOT6[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">82/0</td>
<td>-</td>
<td>in</td>
<td>IOT17[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">81/0</td>
<td>-</td>
<td>in</td>
<td>IOT17[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">80/0</td>
<td>-</td>
<td>in</td>
<td>IOT27[A]</td>
<td>GCLKT_0</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">79/0</td>
<td>-</td>
<td>in</td>
<td>IOT27[B]</td>
<td>GCLKC_0</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">77/1</td>
<td>-</td>
<td>in</td>
<td>IOT30[A]</td>
<td>GCLKT_1</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">76/1</td>
<td>-</td>
<td>in</td>
<td>IOT30[B]</td>
<td>GCLKC_1</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">75/1</td>
<td>-</td>
<td>in</td>
<td>IOT34[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">74/1</td>
<td>-</td>
<td>in</td>
<td>IOT34[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">73/1</td>
<td>-</td>
<td>in</td>
<td>IOT40[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">72/1</td>
<td>-</td>
<td>in</td>
<td>IOT40[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">71/1</td>
<td>-</td>
<td>in</td>
<td>IOT44[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">70/1</td>
<td>i_uart_rx</td>
<td>in</td>
<td>IOT44[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">69/1</td>
<td>o_uart_tx</td>
<td>out</td>
<td>IOT50[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">25/5</td>
<td>-</td>
<td>in</td>
<td>IOB6[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">26/5</td>
<td>-</td>
<td>in</td>
<td>IOB6[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">27/5</td>
<td>-</td>
<td>in</td>
<td>IOB8[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">28/5</td>
<td>-</td>
<td>in</td>
<td>IOB8[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">29/5</td>
<td>-</td>
<td>in</td>
<td>IOB14[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">30/5</td>
<td>-</td>
<td>in</td>
<td>IOB14[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">31/5</td>
<td>-</td>
<td>in</td>
<td>IOB18[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">32/5</td>
<td>-</td>
<td>in</td>
<td>IOB18[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">33/5</td>
<td>-</td>
<td>in</td>
<td>IOB24[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">34/5</td>
<td>-</td>
<td>in</td>
<td>IOB24[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">35/4</td>
<td>-</td>
<td>in</td>
<td>IOB30[A]</td>
<td>GCLKT_4</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">36/4</td>
<td>-</td>
<td>in</td>
<td>IOB30[B]</td>
<td>GCLKC_4</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">37/4</td>
<td>-</td>
<td>in</td>
<td>IOB34[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">38/4</td>
<td>-</td>
<td>in</td>
<td>IOB34[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">39/4</td>
<td>-</td>
<td>in</td>
<td>IOB40[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">40/4</td>
<td>-</td>
<td>in</td>
<td>IOB40[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">42/4</td>
<td>-</td>
<td>in</td>
<td>IOB42[B]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">41/4</td>
<td>-</td>
<td>in</td>
<td>IOB43[A]</td>
<td>-</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">p1/7</td>
<td>-</td>
<td>in</td>
<td>IOL3[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p2/7</td>
<td>-</td>
<td>in</td>
<td>IOL3[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">4/7</td>
<td>i_clk</td>
<td>in</td>
<td>IOL7[A]</td>
<td>LPLL1_T_in</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">p5/7</td>
<td>-</td>
<td>in</td>
<td>IOL8[A]</td>
<td>LPLL1_T_fb</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p6/7</td>
<td>-</td>
<td>in</td>
<td>IOL8[B]</td>
<td>LPLL1_C_fb</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p7/7</td>
<td>-</td>
<td>in</td>
<td>IOL9[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p8/7</td>
<td>-</td>
<td>in</td>
<td>IOL9[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p11/7</td>
<td>-</td>
<td>in</td>
<td>IOL11[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p12/7</td>
<td>-</td>
<td>in</td>
<td>IOL11[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p14/7</td>
<td>-</td>
<td>in</td>
<td>IOL12[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p19/7</td>
<td>-</td>
<td>in</td>
<td>IOL12[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p18/7</td>
<td>-</td>
<td>in</td>
<td>IOL13[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p21/7</td>
<td>-</td>
<td>in</td>
<td>IOL13[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p20/7</td>
<td>-</td>
<td>in</td>
<td>IOL14[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p22/7</td>
<td>-</td>
<td>in</td>
<td>IOL14[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p23/7</td>
<td>-</td>
<td>in</td>
<td>IOL15[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p24/7</td>
<td>-</td>
<td>in</td>
<td>IOL15[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p26/7</td>
<td>-</td>
<td>in</td>
<td>IOL16[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p28/7</td>
<td>-</td>
<td>in</td>
<td>IOL16[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p25/7</td>
<td>-</td>
<td>in</td>
<td>IOL17[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p27/7</td>
<td>-</td>
<td>in</td>
<td>IOL17[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p29/7</td>
<td>-</td>
<td>in</td>
<td>IOL18[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p31/7</td>
<td>-</td>
<td>in</td>
<td>IOL18[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p32/7</td>
<td>-</td>
<td>in</td>
<td>IOL20[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">10/6</td>
<td>-</td>
<td>in</td>
<td>IOL29[A]</td>
<td>GCLKT_6</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">11/6</td>
<td>-</td>
<td>in</td>
<td>IOL29[B]</td>
<td>GCLKC_6</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">p35/6</td>
<td>-</td>
<td>in</td>
<td>IOL30[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p36/6</td>
<td>-</td>
<td>in</td>
<td>IOL30[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p37/6</td>
<td>-</td>
<td>in</td>
<td>IOL35[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p38/6</td>
<td>-</td>
<td>in</td>
<td>IOL35[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p41/6</td>
<td>-</td>
<td>in</td>
<td>IOL39[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p42/6</td>
<td>-</td>
<td>in</td>
<td>IOL39[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">13/6</td>
<td>-</td>
<td>in</td>
<td>IOL45[A]</td>
<td>LPLL2_T_in</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">15/6</td>
<td>o_led[0]</td>
<td>out</td>
<td>IOL47[A]</td>
<td>LPLL2_T_fb</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">16/6</td>
<td>o_led[1]</td>
<td>out</td>
<td>IOL47[B]</td>
<td>LPLL2_C_fb</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">17/6</td>
<td>o_led[2]</td>
<td>out</td>
<td>IOL49[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">18/6</td>
<td>o_led[3]</td>
<td>out</td>
<td>IOL49[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">19/6</td>
<td>o_led[4]</td>
<td>out</td>
<td>IOL51[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">20/6</td>
<td>o_led[5]</td>
<td>out</td>
<td>IOL51[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">p89/2</td>
<td>-</td>
<td>in</td>
<td>IOR3[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p88/2</td>
<td>-</td>
<td>in</td>
<td>IOR3[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p85/2</td>
<td>-</td>
<td>in</td>
<td>IOR4[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p84/2</td>
<td>-</td>
<td>in</td>
<td>IOR5[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p82/2</td>
<td>-</td>
<td>in</td>
<td>IOR5[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p83/2</td>
<td>-</td>
<td>in</td>
<td>IOR6[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p79/2</td>
<td>-</td>
<td>in</td>
<td>IOR9[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p78/2</td>
<td>-</td>
<td>in</td>
<td>IOR9[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p76/2</td>
<td>-</td>
<td>in</td>
<td>IOR11[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p73/2</td>
<td>-</td>
<td>in</td>
<td>IOR11[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p70/2</td>
<td>-</td>
<td>in</td>
<td>IOR12[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p68/2</td>
<td>-</td>
<td>in</td>
<td>IOR12[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p69/2</td>
<td>-</td>
<td>in</td>
<td>IOR13[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p66/2</td>
<td>-</td>
<td>in</td>
<td>IOR13[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p67/2</td>
<td>-</td>
<td>in</td>
<td>IOR14[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p65/2</td>
<td>-</td>
<td>in</td>
<td>IOR14[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p64/2</td>
<td>-</td>
<td>in</td>
<td>IOR15[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p61/2</td>
<td>-</td>
<td>in</td>
<td>IOR15[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p58/2</td>
<td>-</td>
<td>in</td>
<td>IOR16[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p55/2</td>
<td>-</td>
<td>in</td>
<td>IOR16[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p59/2</td>
<td>-</td>
<td>in</td>
<td>IOR17[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p54/2</td>
<td>-</td>
<td>in</td>
<td>IOR17[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p53/2</td>
<td>-</td>
<td>in</td>
<td>IOR18[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p52/2</td>
<td>-</td>
<td>in</td>
<td>IOR18[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">8/2</td>
<td>-</td>
<td>out</td>
<td>IOR25[A]</td>
<td>TDO</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">5/2</td>
<td>-</td>
<td>in</td>
<td>IOR25[B]</td>
<td>TMS</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">6/2</td>
<td>-</td>
<td>in</td>
<td>IOR26[A]</td>
<td>TCK</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">7/2</td>
<td>-</td>
<td>in</td>
<td>IOR26[B]</td>
<td>TDI</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">63/3</td>
<td>-</td>
<td>in</td>
<td>IOR29[A]</td>
<td>GCLKT_3</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">88/3</td>
<td>i_rst_n</td>
<td>in</td>
<td>IOR30[A]</td>
<td>MODE0</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">87/3</td>
<td>-</td>
<td>in</td>
<td>IOR30[B]</td>
<td>MODE1</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">9/3</td>
<td>-</td>
<td>in</td>
<td>IOR31[B]</td>
<td>RECONFIG_N</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">62/3</td>
<td>-</td>
<td>in</td>
<td>IOR33[A]</td>
<td>MI/D7</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">61/3</td>
<td>-</td>
<td>in</td>
<td>IOR33[B]</td>
<td>MO/D6</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">60/3</td>
<td>-</td>
<td>in</td>
<td>IOR34[A]</td>
<td>MCS_N/D5</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">59/3</td>
<td>-</td>
<td>in</td>
<td>IOR34[B]</td>
<td>MCLK/D4</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">57/3</td>
<td>-</td>
<td>in</td>
<td>IOR35[A]</td>
<td>FASTRD_N/D3</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">56/3</td>
<td>-</td>
<td>in</td>
<td>IOR36[A]</td>
<td>SO/D1</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">55/3</td>
<td>-</td>
<td>in</td>
<td>IOR36[B]</td>
<td>SSPI_CS_N/D0</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">54/3</td>
<td>-</td>
<td>in</td>
<td>IOR38[A]</td>
<td>DIN/CLKHOLD_N</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">53/3</td>
<td>-</td>
<td>in</td>
<td>IOR38[B]</td>
<td>DOUT/WE_N</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">52/3</td>
<td>-</td>
<td>in</td>
<td>IOR39[A]</td>
<td>SCLK</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">p49/3</td>
<td>-</td>
<td>in</td>
<td>IOR44[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">p48/3</td>
<td>-</td>
<td>in</td>
<td>IOR44[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>-</td>
<td>UP</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
<td>-</td>
</tr>
<tr>
<td class="label">51/3</td>
<td>-</td>
<td>in</td>
<td>IOR45[A]</td>
<td>RPLL2_T_in</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">49/3</td>
<td>-</td>
<td>in</td>
<td>IOR49[A]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">48/3</td>
<td>-</td>
<td>in</td>
<td>IOR49[B]</td>
<td>-</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
</table>
<br/>
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