25 lines
1.1 KiB
XML
25 lines
1.1 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE gowin-synthesis-project>
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<Project>
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<Version>beta</Version>
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<Device id="GW2AR-18C" package="QFN88" speed="8" partNumber="GW2AR-LV18QN88C8/I7"/>
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<FileList>
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<File path="/Users/car/Projects/hope/alu.v" type="verilog"/>
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<File path="/Users/car/Projects/hope/cpu.v" type="verilog"/>
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<File path="/Users/car/Projects/hope/register_file.v" type="verilog"/>
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<File path="/Users/car/Projects/hope/sequencer.v" type="verilog"/>
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<File path="/Users/car/Projects/hope/sram_srom.v" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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<Option type="global_freq" value="100.000"/>
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<Option type="looplimit" value="2000"/>
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<Option type="output_file" value="/Users/car/Projects/hope/hope/impl/gwsynthesis/hope.vg"/>
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<Option type="print_all_synthesis_warning" value="0"/>
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<Option type="ram_rw_check" value="0"/>
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<Option type="vcc" value="1.0"/>
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<Option type="verilog_language" value="verilog-2001"/>
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<Option type="vhdl_language" value="vhdl-1993"/>
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</OptionList>
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</Project>
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