33 lines
697 B
Systemverilog
33 lines
697 B
Systemverilog
module charram
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#(parameter COLS=80,
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parameter ROWS=60)
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(input i_clk,
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input i_rst,
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input [12:0] i_gen_addr,
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input [12:0] i_cpu_addr,
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input [15:0] i_cpu_data,
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input i_cpu_we,
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output [15:0] o_gen_data,
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output [15:0] o_cpu_data);
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localparam CELLS=COLS*ROWS;
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reg [15:0] cram [0:CELLS-1];
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integer i;
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initial begin
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$readmemh("/Users/car/Projects/hope/cram.hex", cram);
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end
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assign o_gen_data = cram[i_gen_addr];
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assign o_cpu_data = cram[i_cpu_addr];
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always @(posedge i_clk, posedge i_rst) begin
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if (i_rst) begin
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end else if (i_cpu_we) begin
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cram[i_cpu_addr] <= i_cpu_data;
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end
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end
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endmodule
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