46 lines
1.2 KiB
Systemverilog
46 lines
1.2 KiB
Systemverilog
module chargen
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#(parameter CHAR_WIDTH=8,
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parameter CHAR_HEIGHT=8,
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parameter COLS=80,
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parameter ROWS=60)
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(input i_clk,
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input i_rst,
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input i_de,
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input [10:0] i_row,
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input [10:0] i_col,
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input [15:0] i_ram_data,
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output [12:0] o_ram_addr,
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output o_r,
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output o_g,
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output o_b);
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reg [7:0] fontrom [0:2047];
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reg [7:0] glyph_line;
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wire glyph_bit;
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wire [7:0] char_attr;
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wire [7:0] char_char;
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assign o_ram_addr = i_row[10:3] * COLS + i_col[10:3];
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assign glyph_bit = glyph_line[CHAR_WIDTH-1];
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assign char_char = i_ram_data[7:0];
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assign char_attr = i_ram_data[15:8];
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assign o_r = glyph_bit?char_attr[0]:char_attr[3];
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assign o_g = glyph_bit?char_attr[1]:char_attr[4];
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assign o_b = glyph_bit?char_attr[2]:char_attr[5];
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initial begin
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$readmemh("/Users/car/Projects/hope/font.hex", fontrom);
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end
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always @(posedge i_clk, posedge i_rst) begin
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if (i_rst) begin
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glyph_line <= 0;
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end else if (i_col[2:0] == 0) begin
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glyph_line <= fontrom[{char_char, i_row[2:0]}];
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end else begin
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glyph_line <= glyph_line << 1;
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end
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end // always @ (posedge i_clk, posedge i_rst)
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endmodule
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