$OpenBSD: patch-lib_Target_Sparc_SparcInstrAliases_td,v 1.2 2014/09/18 20:19:27 brad Exp $ Sync up the SPARC backend up to commit r203424. r208966 Sparc: disable printing of jmp/call aliases (C++ does it) These aliases are handled entirely in C++ and only having TableGen InstAliases for some of them was confusing LLVM. --- lib/Target/Sparc/SparcInstrAliases.td.orig Sun Mar 2 21:57:39 2014 +++ lib/Target/Sparc/SparcInstrAliases.td Mon Sep 15 15:27:10 2014 @@ -13,32 +13,53 @@ // Instruction aliases for conditional moves. // mov rs2, rd -multiclass cond_mov_alias { - // mov (%icc|%xcc|%fcc0), rs2, rd + // mov (%icc|%xcc), rs2, rd def : InstAlias; - // mov (%icc|%xcc|%fcc0), simm11, rd + // mov (%icc|%xcc), simm11, rd def : InstAlias; - // fmovs (%icc|%xcc|%fcc0), $rs2, $rd + // fmovs (%icc|%xcc), $rs2, $rd def : InstAlias; - // fmovd (%icc|%xcc|%fcc0), $rs2, $rd + // fmovd (%icc|%xcc), $rs2, $rd def : InstAlias; } +// mov rs2, rd +multiclass fpcond_mov_alias { + // mov %fcc[0-3], rs2, rd + def : InstAlias; + + // mov %fcc[0-3], simm11, rd + def : InstAlias; + + // fmovs %fcc[0-3], $rs2, $rd + def : InstAlias; + + // fmovd %fcc[0-3], $rs2, $rd + def : InstAlias; +} + // Instruction aliases for integer conditional branches and moves. multiclass int_cond_alias { @@ -46,15 +67,64 @@ multiclass int_cond_alias { def : InstAlias; + // b,a $imm + def : InstAlias; + + // b %icc, $imm + def : InstAlias, Requires<[HasV9]>; + + // b,pt %icc, $imm + def : InstAlias, Requires<[HasV9]>; + + // b,a %icc, $imm + def : InstAlias, Requires<[HasV9]>; + + // b,a,pt %icc, $imm + def : InstAlias, Requires<[HasV9]>; + + // b,pn %icc, $imm + def : InstAlias, Requires<[HasV9]>; + + // b,a,pn %icc, $imm + def : InstAlias, Requires<[HasV9]>; + // b %xcc, $imm def : InstAlias, Requires<[Is64Bit]>; - defm : cond_mov_alias,pt %xcc, $imm + def : InstAlias, Requires<[Is64Bit]>; + + // b,a %xcc, $imm + def : InstAlias, Requires<[Is64Bit]>; + + // b,a,pt %xcc, $imm + def : InstAlias, Requires<[Is64Bit]>; + + // b,pn %xcc, $imm + def : InstAlias, Requires<[Is64Bit]>; + + // b,a,pn %xcc, $imm + def : InstAlias, Requires<[Is64Bit]>; + + + defm : intcond_mov_alias, Requires<[HasV9]>; - defm : cond_mov_alias, Requires<[Is64Bit]>; @@ -66,6 +136,59 @@ multiclass int_cond_alias { (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, Requires<[Is64Bit, HasHardQuad]>; + // t %icc, rs1 + rs2 + def : InstAlias, + Requires<[HasV9]>; + + // t %icc, rs => t %icc, G0 + rs + def : InstAlias, + Requires<[HasV9]>; + + // t %xcc, rs1 + rs2 + def : InstAlias, + Requires<[HasV9]>; + + // t %xcc, rs => t %xcc, G0 + rs + def : InstAlias, + Requires<[HasV9]>; + + // t rs1 + rs2 => t %icc, rs1 + rs2 + def : InstAlias; + + // t rs=> t %icc, G0 + rs2 + def : InstAlias; + + // t %icc, rs1 + imm + def : InstAlias, + Requires<[HasV9]>; + // t %icc, imm => t %icc, G0 + imm + def : InstAlias, + Requires<[HasV9]>; + // t %xcc, rs1 + imm + def : InstAlias, + Requires<[HasV9]>; + // t %xcc, imm => t %xcc, G0 + imm + def : InstAlias, + Requires<[HasV9]>; + + // t rs1 + imm => t %icc, rs1 + imm + def : InstAlias; + + // t imm => t %icc, G0 + imm + def : InstAlias; + } @@ -76,13 +199,48 @@ multiclass fp_cond_alias { def : InstAlias; - defm : cond_mov_alias, Requires<[HasV9]>; + // fb,a $imm + def : InstAlias; + // fb %fcc0, $imm + def : InstAlias, + Requires<[HasV9]>; + + // fb,pt %fcc0, $imm + def : InstAlias, + Requires<[HasV9]>; + + // fb,a %fcc0, $imm + def : InstAlias, + Requires<[HasV9]>; + + // fb,a,pt %fcc0, $imm + def : InstAlias, + Requires<[HasV9]>; + + // fb,pn %fcc0, $imm + def : InstAlias, + Requires<[HasV9]>; + + // fb,a,pn %fcc0, $imm + def : InstAlias, + Requires<[HasV9]>; + + defm : fpcond_mov_alias, Requires<[HasV9]>; + // fmovq %fcc0, $rs2, $rd - def : InstAlias, + def : InstAlias, Requires<[HasV9, HasHardQuad]>; } @@ -103,6 +261,8 @@ defm : int_cond_alias<"neg", 0b0110>; defm : int_cond_alias<"vc", 0b1111>; defm : int_cond_alias<"vs", 0b0111>; +defm : fp_cond_alias<"a", 0b0000>; +defm : fp_cond_alias<"n", 0b1000>; defm : fp_cond_alias<"u", 0b0111>; defm : fp_cond_alias<"g", 0b0110>; defm : fp_cond_alias<"ug", 0b0101>; @@ -118,16 +278,15 @@ defm : fp_cond_alias<"le", 0b1101>; defm : fp_cond_alias<"ule", 0b1110>; defm : fp_cond_alias<"o", 0b1111>; - // Instruction aliases for JMPL. // jmp addr -> jmpl addr, %g0 -def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr)>; -def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr)>; +def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>; +def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>; // call addr -> jmpl addr, %o7 -def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr)>; -def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr)>; +def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>; +def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>; // retl -> RETL 8 def : InstAlias<"retl", (RETL 8)>; @@ -140,3 +299,27 @@ def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0 // mov simm13, rd -> or %g0, simm13, rd def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; + +// restore -> restore %g0, %g0, %g0 +def : InstAlias<"restore", (RESTORErr G0, G0, G0)>; + +def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>; + +def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>; +def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>; + +def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>; +def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>; + + +def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>; +def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>; +def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>, + Requires<[HasHardQuad]>; + +def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>; +def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1, + DFPRegs:$rs2)>; +def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1, + QFPRegs:$rs2)>, + Requires<[HasHardQuad]>;