diff --git a/lang/verilator/Makefile b/lang/verilator/Makefile
index e955906ef84..2342ba82802 100644
--- a/lang/verilator/Makefile
+++ b/lang/verilator/Makefile
@@ -1,4 +1,4 @@
-# $OpenBSD: Makefile,v 1.1.1.1 2011/11/13 12:44:04 jasper Exp $
+# $OpenBSD: Makefile,v 1.2 2011/11/17 23:33:40 nigel Exp $
 
 COMMENT=	very fast free Verilog HDL simulator
 
@@ -18,6 +18,8 @@ EXTRACT_SUFX=		.tgz
 
 WANTLIB=		c m stdc++
 
+BUILD_DEPENDS +=	devel/bison
+
 CONFIGURE_STYLE=	gnu
 MAKE_FLAGS=		VERILATOR_ROOT=${PREFIX}/share/verilator/ \
 			COPT="${CFLAGS}"
@@ -27,4 +29,4 @@ USE_GMAKE=		Yes
 REGRESS_TARGET=		test
 REGRESS_FLAGS=		VERILATOR_ROOT=${WRKSRC}
 
-.include <bsd.port.mk>
\ No newline at end of file
+.include <bsd.port.mk>