diff --git a/lang/nhc98/patches/patch-src_runtime_Integer_asmlong_h b/lang/nhc98/patches/patch-src_runtime_Integer_asmlong_h
new file mode 100644
index 00000000000..09faaf41a0f
--- /dev/null
+++ b/lang/nhc98/patches/patch-src_runtime_Integer_asmlong_h
@@ -0,0 +1,502 @@
+$OpenBSD: patch-src_runtime_Integer_asmlong_h,v 1.1 2004/07/13 11:38:16 espie Exp $
+--- src/runtime/Integer/asmlong.h.orig	Tue Jul 13 12:38:15 2004
++++ src/runtime/Integer/asmlong.h	Tue Jul 13 12:51:57 2004
+@@ -1,13 +1,13 @@
+ #if defined (__a29k__) || defined (___AM29K__)
+ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("add %1,%4,%5
+-	addc %0,%2,%3"							\
++  __asm__ ("add %1,%4,%5\n"						\
++"	addc %0,%2,%3"							\
+ 	 : "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl)) \
+ 	 : "%r" ((unsigned long int)(ah)), "rI" ((unsigned long int)(bh)), \
+ 	   "%r" ((unsigned long int)(al)), "rI" ((unsigned long int)(bl)))
+ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("sub %1,%4,%5
+-	subc %0,%2,%3"							\
++  __asm__ ("sub %1,%4,%5\n"						\
++"	subc %0,%2,%3"							\
+ 	 : "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl)) \
+ 	 : "r" ((unsigned long int)(ah)), "rI" ((unsigned long int)(bh)), \
+ 	   "r" ((unsigned long int)(al)), "rI" ((unsigned long int)(bl)))
+@@ -31,14 +31,14 @@
+ 
+ #if defined (__arm__)
+ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("adds %1,%4,%5
+-	adc %0,%2,%3"							\
++  __asm__ ("adds %1,%4,%5\n"						\
++"	adc %0,%2,%3"							\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl)) \
+ 	: "%r" ((unsigned long int)(ah)), "rI" ((unsigned long int)(bh)), \
+ 	  "%r" ((unsigned long int)(al)), "rI" ((unsigned long int)(bl)))
+ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("subs %1,%4,%5
+-	sbc %0,%2,%3"							\
++  __asm__ ("subs %1,%4,%5\n"						\
++"	sbc %0,%2,%3"							\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl)) \
+ 	: "r" ((unsigned long int)(ah)), "rI" ((unsigned long int)(bh)), \
+ 	  "r" ((unsigned long int)(al)), "rI" ((unsigned long int)(bl)))
+@@ -46,14 +46,14 @@
+ 
+ #if defined (__gmicro__)
+ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("add.w %5,%1
+-	addx %3,%0"							\
++  __asm__ ("add.w %5,%1\n"						\
++"	addx %3,%0"							\
+        : "=g" ((unsigned long int)(sh)), "=&g" ((unsigned long int)(sl))\
+        : "%0" ((unsigned long int)(ah)), "g" ((unsigned long int)(bh)),	\
+ 	 "%1" ((unsigned long int)(al)), "g" ((unsigned long int)(bl)))
+ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("sub.w %5,%1
+-	subx %3,%0"							\
++  __asm__ ("sub.w %5,%1\n"						\
++"	subx %3,%0"							\
+        : "=g" ((unsigned long int)(sh)), "=&g" ((unsigned long int)(sl))\
+        : "0" ((unsigned long int)(ah)), "g" ((unsigned long int)(bh)),	\
+ 	 "1" ((unsigned long int)(al)), "g" ((unsigned long int)(bl)))
+@@ -74,14 +74,14 @@
+ 
+ #if defined (__hppa)
+ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("add %4,%5,%1
+-        addc %2,%3,%0"				\
++  __asm__ ("add %4,%5,%1\n"			\
++"        addc %2,%3,%0"				\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+ 	: "%r" ((unsigned long int)(ah)), "r" ((unsigned long int)(bh)),\
+ 	  "%r" ((unsigned long int)(al)), "r" ((unsigned long int)(bl)))
+ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("sub %5,%4,%1
+-        subb %3,%2,%0"				\
++  __asm__ ("sub %5,%4,%1\n"			\
++"        subb %3,%2,%0"				\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+ 	: "r" ((unsigned long int)(ah)), "r" ((unsigned long int)(bh)),	\
+ 	  "r" ((unsigned long int)(al)), "r" ((unsigned long int)(bl)))
+@@ -89,14 +89,14 @@
+ 
+ #if defined (__i386__) || defined (__i486__)
+ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("addl %5,%1
+-	adcl %3,%0"							\
++  __asm__ ("addl %5,%1\n"						\
++"	adcl %3,%0"							\
+        : "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+        : "%0" ((unsigned long int)(ah)), "g" ((unsigned long int)(bh)),	\
+ 	 "%1" ((unsigned long int)(al)), "g" ((unsigned long int)(bl)))
+ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("subl %5,%1
+-	sbbl %3,%0"							\
++  __asm__ ("subl %5,%1\n"						\
++"	sbbl %3,%0"							\
+        : "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+        : "0" ((unsigned long int)(ah)), "g" ((unsigned long int)(bh)),	\
+ 	 "1" ((unsigned long int)(al)), "g" ((unsigned long int)(bl)))
+@@ -157,14 +157,14 @@
+ 
+ #if defined (___IBMR2__) /* IBM RS6000 */
+ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("a %1,%4,%5
+-	ae %0,%2,%3"							\
++  __asm__ ("a %1,%4,%5\n"						\
++"	ae %0,%2,%3"							\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+ 	: "%r" ((unsigned long int)(ah)), "r" ((unsigned long int)(bh)),\
+ 	  "%r" ((unsigned long int)(al)), "r" ((unsigned long int)(bl)))
+ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("sf %1,%5,%4
+-	sfe %0,%3,%2"							\
++  __asm__ ("sf %1,%5,%4\n"						\
++"	sfe %0,%3,%2"							\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+ 	: "r" ((unsigned long int)(ah)), "r" ((unsigned long int)(bh)),	\
+ 	  "r" ((unsigned long int)(al)), "r" ((unsigned long int)(bl)))
+@@ -264,32 +264,32 @@
+ 	: "od" ((unsigned long int)(x)), "n" (0))
+ #else /* not mc68020 */
+ #define umul_ppmm(xh, xl, a, b) \
+-  __asm__ ("| Inlined umul_ppmm
+-	movel	%2,d0
+-	movel	%3,d1
+-	movel	d0,d2
+-	swap	d0
+-	movel	d1,d3
+-	swap	d1
+-	movew	d2,d4
+-	mulu	d3,d4
+-	mulu	d1,d2
+-	mulu	d0,d3
+-	mulu	d0,d1
+-	movel	d4,d0
+-	eorw	d0,d0
+-	swap	d0
+-	addl	d0,d2
+-	addl	d3,d2
+-	jcc	1f
+-	addl	#65536,d1
+-1:	swap	d2
+-	moveq	#0,d0
+-	movew	d2,d0
+-	movew	d4,d2
+-	movel	d2,%1
+-	addl	d1,d0
+-	movel	d0,%0"							\
++  __asm__ ("| Inlined umul_ppmm\n"	\
++"	movel	%2,d0\n"		\
++"	movel	%3,d1\n"		\
++"	movel	d0,d2\n"		\
++"	swap	d0\n"			\
++"	movel	d1,d3\n"		\
++"	swap	d1\n"			\
++"	movew	d2,d4\n"		\
++"	mulu	d3,d4\n"		\
++"	mulu	d1,d2\n"		\
++"	mulu	d0,d3\n"		\
++"	mulu	d0,d1\n"		\
++"	movel	d4,d0\n"		\
++"	eorw	d0,d0\n"		\
++"	swap	d0\n"			\
++"	addl	d0,d2\n"		\
++"	addl	d3,d2\n"		\
++"	jcc	1f\n"			\
++"	addl	#65536,d1\n"		\
++"1:	swap	d2\n"			\
++"	moveq	#0,d0\n"		\
++"	movew	d2,d0\n"		\
++"	movew	d4,d2\n"		\
++"	movel	d2,%1\n"		\
++"	addl	d1,d0\n"		\
++"	movel	d0,%0"							\
+        : "=g" ((unsigned long int)(xh)), "=g" ((unsigned long int)(xl))	\
+        :"g" ((unsigned long int)(a)), "g" ((unsigned long int)(b))	\
+        : "d0", "d1", "d2", "d3", "d4")
+@@ -298,14 +298,14 @@
+ 
+ #if defined (__m88000__)
+ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("addu.co %1,%r4,%r5
+-	addu.ci %0,%r2,%r3"						\
++  __asm__ ("addu.co %1,%r4,%r5\n"	\
++"	addu.ci %0,%r2,%r3"						\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+ 	: "%rJ" ((unsigned long int)(ah)), "rJ" ((unsigned long int)(bh)),\
+ 	  "%rJ" ((unsigned long int)(al)), "rJ" ((unsigned long int)(bl)))
+ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("subu.co %1,%r4,%r5
+-	subu.ci %0,%r2,%r3"						\
++  __asm__ ("subu.co %1,%r4,%r5\n"	\
++"	subu.ci %0,%r2,%r3"						\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+ 	: "rJ" ((unsigned long int)(ah)), "rJ" ((unsigned long int)(bh)),\
+ 	  "rJ" ((unsigned long int)(al)), "rJ" ((unsigned long int)(bl)))
+@@ -322,9 +322,9 @@
+ 
+ #if defined (__mips__)
+ #define umul_ppmm(w1, w0, u, v) \
+-  __asm__ ("multu %2,%3
+-	mflo %0
+-	mfhi %1"							\
++  __asm__ ("multu %2,%3\n"	\
++"	mflo %0\n"		\
++"	mfhi %1"							\
+ 	: "=r" ((unsigned long int)(w0)), "=r" ((unsigned long int)(w1))\
+ 	: "r" ((unsigned long int)(u)), "r" ((unsigned long int)(v)))
+ #define UMUL_TIME 5
+@@ -338,11 +338,11 @@
+ 	: "%0" ((unsigned long int)(u)), "g" ((unsigned long int)(v)));	\
+       __w; })
+ #define div_qrnnd(q, r, n1, n0, d) \
+-  __asm__ ("movd %2,r0
+-	movd %3,r1
+-	deid %4,r0
+-	movd r1,%0
+-	movd r0,%1"							\
++  __asm__ ("movd %2,r0\n"	\
++"	movd %3,r1\n"		\
++"	deid %4,r0\n"		\
++"	movd r1,%0\n"		\
++"	movd r0,%1"							\
+ 	: "=g" ((unsigned long int)(q)), "=g" ((unsigned long int)(r))	\
+ 	: "g" ((unsigned long int)(n0)), "g" ((unsigned long int)(n1)),	\
+ 	  "g" ((unsigned long int)(d)) : "r0", "r1")
+@@ -350,23 +350,23 @@
+ 
+ #if defined (__pyr__)
+ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("addw	%5,%1
+-	addwc	%3,%0"							\
++  __asm__ ("addw	%5,%1\n"	\
++"	addwc	%3,%0"							\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+ 	: "%0" ((unsigned long int)(ah)), "g" ((unsigned long int)(bh)),\
+ 	  "%1" ((unsigned long int)(al)), "g" ((unsigned long int)(bl)))
+ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("subw	%5,%1
+-	subwb	%3,%0"							\
++  __asm__ ("subw	%5,%1\n"	\
++"	subwb	%3,%0"							\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+ 	: "0" ((unsigned long int)(ah)), "g" ((unsigned long int)(bh)),	\
+ 	  "1" ((unsigned long int)(al)), "g" ((unsigned long int)(bl)))
+ /* This insn doesn't work on ancient pyramids.  */
+ #define umul_ppmm(w1, w0, u, v) \
+-  __asm__ ("movw %2,tr11
+-	uemul %3,tr10
+-	movw tr10,%0
+-	movw tr11,%1"							\
++  __asm__ ("movw %2,tr11\n"	\
++"	uemul %3,tr10\n"	\
++"	movw tr10,%0\n"		\
++"	movw tr11,%1"							\
+ 	: "=r" ((unsigned long int)(w1)), "=r" ((unsigned long int)(w0))\
+ 	: "r" ((unsigned long int)(u)), "r" ((unsigned long int)(v))	\
+ 	: "tr10", "tr11")
+@@ -374,14 +374,14 @@
+ 
+ #if defined (__ibm032__) /* RT/ROMP */
+ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("a %1,%5
+-	ae %0,%3"							\
++  __asm__ ("a %1,%5\n"		\
++"	ae %0,%3"							\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+ 	: "%0" ((unsigned long int)(ah)), "r" ((unsigned long int)(bh)),\
+ 	  "%1" ((unsigned long int)(al)), "r" ((unsigned long int)(bl)))
+ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("s %1,%5
+-	se %0,%3"							\
++  __asm__ ("s %1,%5\n"		\
++"	se %0,%3"							\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+ 	: "0" ((unsigned long int)(ah)), "r" ((unsigned long int)(bh)),	\
+ 	  "1" ((unsigned long int)(al)), "r" ((unsigned long int)(bl)))
+@@ -389,26 +389,26 @@
+   do {									\
+     unsigned long int __m0 = (m0), __m1 = (m1);				\
+     __asm__ (								\
+-       "s	r2,r2
+-	mts	r10,%2
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	m	r2,%3
+-	cas	%0,r2,r0
+-	mfs	r10,%1"							\
++       "s	r2,r2\n"	\
++"	mts	r10,%2\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	m	r2,%3\n"	\
++"	cas	%0,r2,r0\n"	\
++"	mfs	r10,%1"							\
+        : "=r" ((unsigned long int)(ph)), "=r" ((unsigned long int)(pl))	\
+        : "%r" (__m0), "r" (__m1)					\
+        : "r2");								\
+@@ -433,14 +433,14 @@
+ 
+ #if defined (__sparc__)
+ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("addcc %4,%5,%1
+-	addx %2,%3,%0"							\
++  __asm__ ("addcc %4,%5,%1\n"	\
++"	addx %2,%3,%0"							\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+ 	: "%r" ((unsigned long int)(ah)), "rI" ((unsigned long int)(bh)),\
+ 	  "%r" ((unsigned long int)(al)), "rI" ((unsigned long int)(bl)))
+ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("subcc %4,%5,%1
+-	subx %2,%3,%0"							\
++  __asm__ ("subcc %4,%5,%1\n"	\
++"	subx %2,%3,%0"							\
+ 	: "=r" ((unsigned long int)(sh)), "=&r" ((unsigned long int)(sl))\
+ 	: "r" ((unsigned long int)(ah)), "rI" ((unsigned long int)(bh)),\
+ 	  "r" ((unsigned long int)(al)), "rI" ((unsigned long int)(bl)))
+@@ -458,46 +458,46 @@
+ /* SPARC without integer multiplication and divide instructions.
+    (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
+ #define umul_ppmm(w1, w0, u, v) \
+-  __asm__ ("! Inlined umul_ppmm
+-	wr	%%g0,%2,%%y	! SPARC has 0-3 delay insn after a wr
+-	sra	%3,31,%%g2	! Don't move this insn
+-	and	%2,%%g2,%%g2	! Don't move this insn
+-	andcc	%%g0,0,%%g1	! Don't move this insn
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,%3,%%g1
+-	mulscc	%%g1,0,%%g1
+-	add	%%g1,%%g2,%0
+-	rd	%%y,%1"							\
++  __asm__ ("! Inlined umul_ppmm\n"					\
++"	wr	%%g0,%2,%%y	! SPARC has 0-3 delay insn after a wr\n"\
++"	sra	%3,31,%%g2	! Don't move this insn\n"		\
++"	and	%2,%%g2,%%g2	! Don't move this insn\n"		\
++"	andcc	%%g0,0,%%g1	! Don't move this insn\n"		\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,%3,%%g1\n"						\
++"	mulscc	%%g1,0,%%g1\n"						\
++"	add	%%g1,%%g2,%0\n"						\
++"	rd	%%y,%1"							\
+ 	: "=r" ((unsigned long int)(w1)), "=r" ((unsigned long int)(w0))\
+ 	: "%rI" ((unsigned long int)(u)), "r" ((unsigned long int)(v))	\
+        : "%g1", "%g2")
+@@ -505,30 +505,30 @@
+ /* It's quite necessary to add this much assembler for the sparc.
+    The default udiv_qrnnd (in C) is more than 10 times slower!  */
+ #define udiv_qrnnd(q, r, n1, n0, d) \
+-  __asm__ ("! Inlined udiv_qrnnd
+-	mov	32,%%g1
+-	subcc	%1,%2,%%g0
+-1:	bcs	5f
+-	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb
+-	sub	%1,%2,%1	! this kills msb of n
+-	addx	%1,%1,%1	! so this can't give carry
+-	subcc	%%g1,1,%%g1
+-2:	bne	1b
+-	 subcc	%1,%2,%%g0
+-	bcs	3f
+-	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb
+-	b	3f
+-	 sub	%1,%2,%1	! this kills msb of n
+-4:	sub	%1,%2,%1
+-5:	addxcc	%1,%1,%1
+-	bcc	2b
+-	 subcc	%%g1,1,%%g1
+-! Got carry from n.  Subtract next step to cancel this carry.
+-	bne	4b
+-	 addcc	%0,%0,%0	! shift n1n0 and a 0-bit in lsb
+-	sub	%1,%2,%1
+-3:	xnor	%0,0,%0
+-	! End of inline udiv_qrnnd"					\
++  __asm__ ("! Inlined udiv_qrnnd\n"					\
++"	mov	32,%%g1\n"						\
++"	subcc	%1,%2,%%g0\n"						\
++"1:	bcs	5f\n"							\
++"	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb\n"	\
++"	sub	%1,%2,%1	! this kills msb of n\n"		\
++"	addx	%1,%1,%1	! so this can't give carry\n"		\
++"	subcc	%%g1,1,%%g1\n"						\
++"2:	bne	1b\n"							\
++"	 subcc	%1,%2,%%g0\n"						\
++"	bcs	3f\n"							\
++"	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb\n"	\
++"	b	3f\n"							\
++"	 sub	%1,%2,%1	! this kills msb of n\n"		\
++"4:	sub	%1,%2,%1\n"						\
++"5:	addxcc	%1,%1,%1\n"						\
++"	bcc	2b\n"							\
++"	 subcc	%%g1,1,%%g1\n"						\
++"! Got carry from n.  Subtract next step to cancel this carry.\n"	\
++"	bne	4b\n"							\
++"	 addcc	%0,%0,%0	! shift n1n0 and a 0-bit in lsb\n"	\
++"	sub	%1,%2,%1\n"						\
++"3:	xnor	%0,0,%0\n"						\
++"	! End of inline udiv_qrnnd"					\
+ 	: "=r&" ((unsigned long int)(q)), "=r&" ((unsigned long int)(r))\
+ 	: "r" ((unsigned long int)(d)), "1" ((unsigned long int)(n1)),	\
+ 	  "0" ((unsigned long int)(n0)) : "%g1")
+@@ -538,14 +538,14 @@
+ 
+ #if defined (__vax__)
+ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("addl2 %5,%1
+-	adwc %3,%0"							\
++  __asm__ ("addl2 %5,%1\n"	\
++"	adwc %3,%0"							\
+ 	: "=g" ((unsigned long int)(sh)), "=&g" ((unsigned long int)(sl))\
+ 	: "%0" ((unsigned long int)(ah)), "g" ((unsigned long int)(bh)),\
+ 	  "%1" ((unsigned long int)(al)), "g" ((unsigned long int)(bl)))
+ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+-  __asm__ ("subl2 %5,%1
+-	sbwc %3,%0"							\
++  __asm__ ("subl2 %5,%1\n"	\
++"	sbwc %3,%0"							\
+ 	: "=g" ((unsigned long int)(sh)), "=&g" ((unsigned long int)(sl))\
+ 	: "0" ((unsigned long int)(ah)), "g" ((unsigned long int)(bh)),	\
+ 	  "1" ((unsigned long int)(al)), "g" ((unsigned long int)(bl)))