From 544646f4819589968978da33a4add9d5430ac7c0 Mon Sep 17 00:00:00 2001 From: sthen Date: Mon, 10 Dec 2012 15:01:56 +0000 Subject: [PATCH] add hppa-only patch from upstream; build was broken, reported by landry@ --- .../coreutils/patches/patch-src_longlong_h | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 sysutils/coreutils/patches/patch-src_longlong_h diff --git a/sysutils/coreutils/patches/patch-src_longlong_h b/sysutils/coreutils/patches/patch-src_longlong_h new file mode 100644 index 00000000000..ce6d22709fb --- /dev/null +++ b/sysutils/coreutils/patches/patch-src_longlong_h @@ -0,0 +1,28 @@ +$OpenBSD: patch-src_longlong_h,v 1.1 2012/12/10 15:01:56 sthen Exp $ + +http://git.savannah.gnu.org/gitweb/?p=coreutils.git;a=commitdiff;h=da1329e7 + +* src/longlong.h: Restrict some HPPA assembly variants to PA RISC V2.0. +Note we also avoid this assembly for ilp32 runtimes, since even though +the assembly is accepted there, it's not safe as the context can get +clobbered between the 'add' and 'add,dc'. +This fixes a compile failure with newer HPPA systems with default +GCC CPU options. + +--- src/longlong.h.orig Mon Dec 10 14:59:53 2012 ++++ src/longlong.h Mon Dec 10 15:00:25 2012 +@@ -679,7 +679,13 @@ extern UWtype __MPN(udiv_qrnnd) (UWtype *, UWtype, UWt + /* These macros are for ABI=2.0w. In ABI=2.0n they can't be used, since GCC + (3.2) puts longlong into two adjacent 32-bit registers. Presumably this + is just a case of no direct support for 2.0n but treating it like 1.0. */ +-#if defined (__hppa) && W_TYPE_SIZE == 64 && ! defined (_LONG_LONG_LIMB) ++#if defined (__hppa) && W_TYPE_SIZE == 64 && ! defined (_LONG_LONG_LIMB) \ ++ && defined (_PA_RISC2_0) && defined (_LP64) ++/* Note the _PA_RISC2_0 above is to exclude this code from GCC with ++ default -march options which doesn't support these instructions. ++ Also the width check for 'long' is to avoid ilp32 runtimes where ++ GNU/Linux and narrow HP-UX kernels are known to have issues with ++ clobbering of context between the add and add,dc instructions. */ + #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + __asm__ ("add%I5 %5,%r4,%1\n\tadd,dc %r2,%r3,%0" \ + : "=r" (sh), "=&r" (sl) \