2 ExternalFile applicationType IVERILOG Label vdp externalInputs i_clk,i_rst Width 8 externalOutputs o_r,o_g,o_b,o_hsync,o_vsync iverilogOptions /Users/car/Projects/hope/chargen.sv /Users/car/Projects/hope/charram.sv /Users/car/Projects/hope/vga_timing_gen.sv CodeFile /Users/car/Projects/hope/vdp.sv Clock runRealTime true Frequency 2147483647 Reset invertOutput false VGA