Timing Messages

Report Title	Timing Analysis Report
Design File	/Users/car/Projects/hope/hope/impl/gwsynthesis/hope.vg
Physical Constraints File	/Users/car/Projects/hope/tangnano20k.cst
Timing Constraint File	/Users/car/Projects/hope/tangnano20k.sdc
Tool Version	V1.9.11.03 Education
Part Number	GW2AR-LV18QN88C8/I7
Device	GW2AR-18
Device Version	C
Created Time	Fri Feb 20 01:45:30 2026
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	1081
Numbers of Endpoints Analyzed	698
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	i_clk	Base	37.040	26.998	0.000	18.518			i_clk

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	i_clk	26.998(MHz)	36.912(MHz)	19	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
i_clk	Setup	0.000	0
i_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -from_clock [get_clocks {i_clk}] -to_clock [get_clocks {i_clk}] -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	9.949	microcode_rom_microcode_rom_0_0_s/DO[11]	microcode_rom_microcode_rom_0_0_s/AD[8]	i_clk:[R]	i_clk:[R]	37.040	0.000	27.057
2	10.031	microcode_rom_microcode_rom_0_0_s/DO[11]	microcode_rom_microcode_rom_0_0_s/AD[13]	i_clk:[R]	i_clk:[R]	37.040	0.000	26.974
3	10.051	microcode_rom_microcode_rom_0_0_s/DO[11]	microcode_rom_microcode_rom_0_0_s/AD[10]	i_clk:[R]	i_clk:[R]	37.040	0.000	26.955
4	10.132	microcode_rom_microcode_rom_0_0_s/DO[11]	microcode_rom_microcode_rom_0_0_s/AD[5]	i_clk:[R]	i_clk:[R]	37.040	0.000	26.873
5	10.384	microcode_rom_microcode_rom_0_0_s/DO[11]	microcode_rom_microcode_rom_0_0_s/AD[6]	i_clk:[R]	i_clk:[R]	37.040	0.000	26.622
6	10.403	microcode_rom_microcode_rom_0_0_s/DO[11]	microcode_rom_microcode_rom_0_0_s/AD[12]	i_clk:[R]	i_clk:[R]	37.040	0.000	26.602
7	10.518	microcode_rom_microcode_rom_0_0_s/DO[11]	microcode_rom_microcode_rom_0_0_s/AD[11]	i_clk:[R]	i_clk:[R]	37.040	0.000	26.487
8	10.518	microcode_rom_microcode_rom_0_0_s/DO[11]	microcode_rom_microcode_rom_0_0_s/AD[7]	i_clk:[R]	i_clk:[R]	37.040	0.000	26.487
9	10.539	microcode_rom_microcode_rom_0_0_s/DO[11]	microcode_rom_microcode_rom_0_0_s/AD[9]	i_clk:[R]	i_clk:[R]	37.040	0.000	26.467
10	11.010	microcode_rom_microcode_rom_0_0_s/DO[11]	sequencer_inst/pc_4_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	25.995
11	11.177	microcode_rom_microcode_rom_0_0_s/DO[11]	sequencer_inst/pc_3_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	25.828
12	11.252	microcode_rom_microcode_rom_0_0_s/DO[11]	sequencer_inst/pc_8_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	25.753
13	11.305	microcode_rom_microcode_rom_0_0_s/DO[11]	sequencer_inst/pc_6_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	25.700
14	11.343	microcode_rom_microcode_rom_0_0_s/DO[11]	sequencer_inst/pc_2_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	25.662
15	11.404	microcode_rom_microcode_rom_0_0_s/DO[11]	sequencer_inst/pc_7_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	25.601
16	11.416	microcode_rom_microcode_rom_0_0_s/DO[11]	sequencer_inst/pc_0_s2/D	i_clk:[R]	i_clk:[R]	37.040	0.000	25.589
17	11.503	microcode_rom_microcode_rom_0_0_s/DO[11]	sequencer_inst/pc_1_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	25.502
18	11.603	microcode_rom_microcode_rom_0_0_s/DO[11]	sequencer_inst/pc_5_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	25.402
19	16.152	microcode_rom_microcode_rom_0_0_s/DO[11]	register_file_inst/data_registers[0]_10_s1/D	i_clk:[R]	i_clk:[R]	37.040	0.000	20.853
20	16.196	microcode_rom_microcode_rom_0_0_s/DO[11]	register_file_inst/data_registers[1]_10_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	20.809
21	16.345	microcode_rom_microcode_rom_0_0_s/DO[11]	register_file_inst/data_registers[2]_10_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	20.660
22	16.761	microcode_rom_microcode_rom_0_0_s/DO[11]	register_file_inst/data_registers[0]_24_s1/D	i_clk:[R]	i_clk:[R]	37.040	0.000	20.244
23	16.852	microcode_rom_microcode_rom_0_0_s/DO[11]	register_file_inst/data_registers[2]_24_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	20.153
24	16.921	microcode_rom_microcode_rom_0_0_s/DO[11]	register_file_inst/data_registers[2]_7_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	20.084
25	16.921	microcode_rom_microcode_rom_0_0_s/DO[11]	register_file_inst/data_registers[1]_7_s0/D	i_clk:[R]	i_clk:[R]	37.040	0.000	20.084

Hold Paths Table

Report Command:report_timing -hold -from_clock [get_clocks {i_clk}] -to_clock [get_clocks {i_clk}] -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.327	register_file_inst/data_registers[0]_1_s1/Q	sram_srom_inst/sram0_sram0_0_0_s/DI[1]	i_clk:[R]	i_clk:[R]	0.000	0.000	0.576
2	0.341	register_file_inst/data_registers[0]_0_s1/Q	sram_srom_inst/sram0_sram0_0_0_s/DI[0]	i_clk:[R]	i_clk:[R]	0.000	0.000	0.590
3	0.427	sequencer_inst/pc_1_s0/Q	sequencer_inst/pc_1_s0/D	i_clk:[R]	i_clk:[R]	0.000	0.000	0.438
4	0.427	sequencer_inst/pc_6_s0/Q	sequencer_inst/pc_6_s0/D	i_clk:[R]	i_clk:[R]	0.000	0.000	0.438
5	0.428	sequencer_inst/pc_7_s0/Q	sequencer_inst/pc_7_s0/D	i_clk:[R]	i_clk:[R]	0.000	0.000	0.439
6	0.429	sequencer_inst/pc_3_s0/Q	sequencer_inst/pc_3_s0/D	i_clk:[R]	i_clk:[R]	0.000	0.000	0.440
7	0.485	sequencer_inst/pc_0_s2/Q	sequencer_inst/pc_0_s2/D	i_clk:[R]	i_clk:[R]	0.000	0.000	0.496
8	0.485	sequencer_inst/pc_2_s0/Q	sequencer_inst/pc_2_s0/D	i_clk:[R]	i_clk:[R]	0.000	0.000	0.496
9	0.514	register_file_inst/data_registers[0]_7_s1/Q	sram_srom_inst/sram0_sram0_0_1_s/DI[3]	i_clk:[R]	i_clk:[R]	0.000	0.000	0.763
10	0.542	sequencer_inst/pc_4_s0/Q	sequencer_inst/pc_4_s0/D	i_clk:[R]	i_clk:[R]	0.000	0.000	0.553
11	0.546	sequencer_inst/pc_8_s0/Q	sequencer_inst/pc_8_s0/D	i_clk:[R]	i_clk:[R]	0.000	0.000	0.557
12	0.558	register_file_inst/data_registers[0]_2_s1/Q	sram_srom_inst/sram1_sram1_0_0_s/DI[2]	i_clk:[R]	i_clk:[R]	0.000	0.000	0.807
13	0.560	sequencer_inst/pc_5_s0/Q	sequencer_inst/pc_5_s0/D	i_clk:[R]	i_clk:[R]	0.000	0.000	0.571
14	0.571	register_file_inst/data_registers[0]_2_s1/Q	sram_srom_inst/sram0_sram0_0_0_s/DI[2]	i_clk:[R]	i_clk:[R]	0.000	0.000	0.820
15	0.612	register_file_inst/data_registers[0]_3_s1/Q	sram_srom_inst/sram0_sram0_0_0_s/DI[3]	i_clk:[R]	i_clk:[R]	0.000	0.000	0.861
16	0.651	register_file_inst/data_registers[0]_4_s1/Q	sram_srom_inst/sram0_sram0_0_1_s/DI[0]	i_clk:[R]	i_clk:[R]	0.000	0.000	0.900
17	0.721	register_file_inst/data_registers[0]_8_s1/Q	sram_srom_inst/sram1_sram1_0_0_s/DI[0]	i_clk:[R]	i_clk:[R]	0.000	0.000	0.970
18	0.837	register_file_inst/data_registers[0]_1_s1/Q	sram_srom_inst/sram1_sram1_0_0_s/DI[1]	i_clk:[R]	i_clk:[R]	0.000	0.000	1.086
19	0.846	register_file_inst/data_registers[0]_1_s1/Q	sram_srom_inst/sram2_sram2_0_0_s/DI[1]	i_clk:[R]	i_clk:[R]	0.000	0.000	1.095
20	0.848	register_file_inst/data_registers[0]_16_s1/Q	sram_srom_inst/sram2_sram2_0_0_s/DI[0]	i_clk:[R]	i_clk:[R]	0.000	0.000	1.097
21	0.851	register_file_inst/data_registers[0]_20_s1/Q	sram_srom_inst/sram2_sram2_0_1_s/DI[0]	i_clk:[R]	i_clk:[R]	0.000	0.000	1.100
22	0.863	register_file_inst/data_registers[0]_2_s1/Q	sram_srom_inst/sram3_sram3_0_0_s/DI[2]	i_clk:[R]	i_clk:[R]	0.000	0.000	1.112
23	0.890	register_file_inst/data_registers[0]_19_s1/Q	sram_srom_inst/sram2_sram2_0_0_s/DI[3]	i_clk:[R]	i_clk:[R]	0.000	0.000	1.139
24	0.891	sram_srom_inst/mdata_6_s0/Q	register_file_inst/data_registers[0]_6_s1/D	i_clk:[R]	i_clk:[R]	0.000	0.000	0.902
25	0.896	register_file_inst/data_registers[0]_11_s1/Q	sram_srom_inst/sram1_sram1_0_0_s/DI[3]	i_clk:[R]	i_clk:[R]	0.000	0.000	1.145

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	15.323	16.323	1.000	Low Pulse Width	i_clk	strobe_s0
2	15.323	16.323	1.000	Low Pulse Width	i_clk	o_led_5_s2
3	15.323	16.323	1.000	Low Pulse Width	i_clk	o_led_3_s1
4	15.323	16.323	1.000	Low Pulse Width	i_clk	microcode_rom_microcode_rom_0_0_s
5	15.323	16.323	1.000	Low Pulse Width	i_clk	register_file_inst/data_registers[1]_24_s0
6	15.323	16.323	1.000	Low Pulse Width	i_clk	register_file_inst/data_registers[1]_8_s0
7	15.323	16.323	1.000	Low Pulse Width	i_clk	register_file_inst/data_registers[2]_8_s0
8	15.323	16.323	1.000	Low Pulse Width	i_clk	sram_srom_inst/mdata_21_s0
9	15.323	16.323	1.000	Low Pulse Width	i_clk	sram_srom_inst/mdata_20_s0
10	15.323	16.323	1.000	Low Pulse Width	i_clk	register_file_inst/data_registers[2]_7_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -from_clock [get_clocks {i_clk}] -to_clock [get_clocks {i_clk}] -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	9.949
Data Arrival Time	32.386
Data Required Time	42.335
From	microcode_rom_microcode_rom_0_0_s
To	microcode_rom_microcode_rom_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.766	0.617	tNET	FF	1	R34C26[3][B]	sequencer_inst/seq_y_3_s0/I0
31.321	0.555	tINS	FF	1	R34C26[3][B]	sequencer_inst/seq_y_3_s0/F
32.386	1.065	tNET	FF	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/AD[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
42.335	-0.035	tSu		1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.909, 44.015%; route: 12.888, 47.632%; tC2Q: 2.260, 8.353%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path2

Path Summary:

Slack	10.031
Data Arrival Time	32.304
Data Required Time	42.335
From	microcode_rom_microcode_rom_0_0_s
To	microcode_rom_microcode_rom_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.620	0.470	tNET	FF	1	R33C27[0][A]	sequencer_inst/seq_y_8_s0/I3
31.073	0.453	tINS	FF	1	R33C27[0][A]	sequencer_inst/seq_y_8_s0/F
32.304	1.231	tNET	FF	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/AD[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
42.335	-0.035	tSu		1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.807, 43.771%; route: 12.907, 47.851%; tC2Q: 2.260, 8.378%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path3

Path Summary:

Slack	10.051
Data Arrival Time	32.284
Data Required Time	42.335
From	microcode_rom_microcode_rom_0_0_s
To	microcode_rom_microcode_rom_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.766	0.617	tNET	FF	1	R34C26[3][A]	sequencer_inst/seq_y_5_s0/I0
31.219	0.453	tINS	FF	1	R34C26[3][A]	sequencer_inst/seq_y_5_s0/F
32.284	1.065	tNET	FF	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/AD[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
42.335	-0.035	tSu		1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.807, 43.803%; route: 12.888, 47.812%; tC2Q: 2.260, 8.384%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path4

Path Summary:

Slack	10.132
Data Arrival Time	32.203
Data Required Time	42.335
From	microcode_rom_microcode_rom_0_0_s
To	microcode_rom_microcode_rom_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.369	0.220	tNET	FF	1	R33C28[0][B]	sequencer_inst/seq_y_0_s0/I2
30.822	0.453	tINS	FF	1	R33C28[0][B]	sequencer_inst/seq_y_0_s0/F
32.203	1.381	tNET	FF	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/AD[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
42.335	-0.035	tSu		1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.807, 43.936%; route: 12.806, 47.655%; tC2Q: 2.260, 8.410%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path5

Path Summary:

Slack	10.384
Data Arrival Time	31.951
Data Required Time	42.335
From	microcode_rom_microcode_rom_0_0_s
To	microcode_rom_microcode_rom_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.369	0.220	tNET	FF	1	R33C28[2][B]	sequencer_inst/seq_y_1_s0/I1
30.886	0.517	tINS	FF	1	R33C28[2][B]	sequencer_inst/seq_y_1_s0/F
31.951	1.065	tNET	FF	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/AD[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
42.335	-0.035	tSu		1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.871, 44.592%; route: 12.491, 46.919%; tC2Q: 2.260, 8.489%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path6

Path Summary:

Slack	10.403
Data Arrival Time	31.932
Data Required Time	42.335
From	microcode_rom_microcode_rom_0_0_s
To	microcode_rom_microcode_rom_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[0][B]	sequencer_inst/n28_s2/I2
30.159	0.462	tINS	FR	2	R34C28[0][B]	sequencer_inst/n28_s2/F
30.161	0.003	tNET	RR	1	R34C28[2][B]	sequencer_inst/seq_y_7_s0/I2
30.716	0.555	tINS	RF	1	R34C28[2][B]	sequencer_inst/seq_y_7_s0/F
31.932	1.215	tNET	FF	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/AD[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
42.335	-0.035	tSu		1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.918, 44.800%; route: 12.424, 46.704%; tC2Q: 2.260, 8.495%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path7

Path Summary:

Slack	10.518
Data Arrival Time	31.816
Data Required Time	42.335
From	microcode_rom_microcode_rom_0_0_s
To	microcode_rom_microcode_rom_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.176	0.026	tNET	FF	1	R34C28[1][B]	sequencer_inst/seq_y_6_s0/I0
30.629	0.453	tINS	FF	1	R34C28[1][B]	sequencer_inst/seq_y_6_s0/F
31.816	1.187	tNET	FF	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/AD[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
42.335	-0.035	tSu		1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.807, 44.577%; route: 12.420, 46.891%; tC2Q: 2.260, 8.533%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path8

Path Summary:

Slack	10.518
Data Arrival Time	31.816
Data Required Time	42.335
From	microcode_rom_microcode_rom_0_0_s
To	microcode_rom_microcode_rom_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.176	0.026	tNET	FF	1	R34C28[2][A]	sequencer_inst/seq_y_2_s0/I2
30.629	0.453	tINS	FF	1	R34C28[2][A]	sequencer_inst/seq_y_2_s0/F
31.816	1.187	tNET	FF	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/AD[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
42.335	-0.035	tSu		1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.807, 44.577%; route: 12.420, 46.891%; tC2Q: 2.260, 8.533%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path9

Path Summary:

Slack	10.539
Data Arrival Time	31.796
Data Required Time	42.335
From	microcode_rom_microcode_rom_0_0_s
To	microcode_rom_microcode_rom_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.360	0.210	tNET	FF	1	R34C27[2][B]	sequencer_inst/seq_y_4_s0/I2
30.731	0.371	tINS	FF	1	R34C27[2][B]	sequencer_inst/seq_y_4_s0/F
31.796	1.065	tNET	FF	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/AD[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
42.335	-0.035	tSu		1	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.725, 44.301%; route: 12.482, 47.160%; tC2Q: 2.260, 8.539%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path10

Path Summary:

Slack	11.010
Data Arrival Time	31.325
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	sequencer_inst/pc_4_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.863	0.713	tNET	FF	1	R33C26[1][B]	sequencer_inst/n31_s0/I3
31.325	0.462	tINS	FR	1	R33C26[1][B]	sequencer_inst/n31_s0/F
31.325	0.000	tNET	RR	1	R33C26[1][B]	sequencer_inst/pc_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R33C26[1][B]	sequencer_inst/pc_4_s0/CLK
42.334	-0.035	tSu		1	R33C26[1][B]	sequencer_inst/pc_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.816, 45.454%; route: 11.919, 45.852%; tC2Q: 2.260, 8.694%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path11

Path Summary:

Slack	11.177
Data Arrival Time	31.158
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	sequencer_inst/pc_3_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.609	0.459	tNET	FF	1	R34C26[0][A]	sequencer_inst/n32_s0/I0
31.158	0.549	tINS	FR	1	R34C26[0][A]	sequencer_inst/n32_s0/F
31.158	0.000	tNET	RR	1	R34C26[0][A]	sequencer_inst/pc_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R34C26[0][A]	sequencer_inst/pc_3_s0/CLK
42.334	-0.035	tSu		1	R34C26[0][A]	sequencer_inst/pc_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.903, 46.085%; route: 11.665, 45.165%; tC2Q: 2.260, 8.750%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path12

Path Summary:

Slack	11.252
Data Arrival Time	31.082
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	sequencer_inst/pc_8_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.620	0.470	tNET	FF	1	R33C27[1][B]	sequencer_inst/n27_s0/I3
31.082	0.462	tINS	FR	1	R33C27[1][B]	sequencer_inst/n27_s0/F
31.082	0.000	tNET	RR	1	R33C27[1][B]	sequencer_inst/pc_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R33C27[1][B]	sequencer_inst/pc_8_s0/CLK
42.334	-0.035	tSu		1	R33C27[1][B]	sequencer_inst/pc_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.816, 45.882%; route: 11.677, 45.342%; tC2Q: 2.260, 8.776%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path13

Path Summary:

Slack	11.305
Data Arrival Time	31.029
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	sequencer_inst/pc_6_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[0][A]	sequencer_inst/n29_s2/I2
30.150	0.453	tINS	FF	2	R34C28[0][A]	sequencer_inst/n29_s2/F
30.567	0.418	tNET	FF	1	R34C27[1][A]	sequencer_inst/n29_s0/I3
31.029	0.462	tINS	FR	1	R34C27[1][A]	sequencer_inst/n29_s0/F
31.029	0.000	tNET	RR	1	R34C27[1][A]	sequencer_inst/pc_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R34C27[1][A]	sequencer_inst/pc_6_s0/CLK
42.334	-0.035	tSu		1	R34C27[1][A]	sequencer_inst/pc_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.816, 45.977%; route: 11.624, 45.229%; tC2Q: 2.260, 8.794%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path14

Path Summary:

Slack	11.343
Data Arrival Time	30.991
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	sequencer_inst/pc_2_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.620	0.470	tNET	FF	1	R33C27[2][A]	sequencer_inst/n33_s0/I3
30.991	0.371	tINS	FF	1	R33C27[2][A]	sequencer_inst/n33_s0/F
30.991	0.000	tNET	FF	1	R33C27[2][A]	sequencer_inst/pc_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R33C27[2][A]	sequencer_inst/pc_2_s0/CLK
42.334	-0.035	tSu		1	R33C27[2][A]	sequencer_inst/pc_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.725, 45.691%; route: 11.677, 45.503%; tC2Q: 2.260, 8.807%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path15

Path Summary:

Slack	11.404
Data Arrival Time	30.930
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	sequencer_inst/pc_7_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.360	0.210	tNET	FF	1	R34C27[0][A]	sequencer_inst/n28_s0/I0
30.930	0.570	tINS	FR	1	R34C27[0][A]	sequencer_inst/n28_s0/F
30.930	0.000	tNET	RR	1	R34C27[0][A]	sequencer_inst/pc_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R34C27[0][A]	sequencer_inst/pc_7_s0/CLK
42.334	-0.035	tSu		1	R34C27[0][A]	sequencer_inst/pc_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.924, 46.577%; route: 11.417, 44.596%; tC2Q: 2.260, 8.828%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path16

Path Summary:

Slack	11.416
Data Arrival Time	30.918
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	sequencer_inst/pc_0_s2
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.369	0.220	tNET	FF	1	R33C28[2][A]	sequencer_inst/n35_s8/I2
30.918	0.549	tINS	FR	1	R33C28[2][A]	sequencer_inst/n35_s8/F
30.918	0.000	tNET	RR	1	R33C28[2][A]	sequencer_inst/pc_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R33C28[2][A]	sequencer_inst/pc_0_s2/CLK
42.334	-0.035	tSu		1	R33C28[2][A]	sequencer_inst/pc_0_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.903, 46.516%; route: 11.426, 44.652%; tC2Q: 2.260, 8.832%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path17

Path Summary:

Slack	11.503
Data Arrival Time	30.831
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	sequencer_inst/pc_1_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.369	0.220	tNET	FF	1	R33C28[1][A]	sequencer_inst/n34_s0/I3
30.831	0.462	tINS	FR	1	R33C28[1][A]	sequencer_inst/n34_s0/F
30.831	0.000	tNET	RR	1	R33C28[1][A]	sequencer_inst/pc_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R33C28[1][A]	sequencer_inst/pc_1_s0/CLK
42.334	-0.035	tSu		1	R33C28[1][A]	sequencer_inst/pc_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.816, 46.334%; route: 11.426, 44.804%; tC2Q: 2.260, 8.862%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path18

Path Summary:

Slack	11.603
Data Arrival Time	30.731
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	sequencer_inst/pc_5_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[4]
21.258	0.955	tNET	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/I0
21.629	0.371	tINS	FF	1	R29C29[2][A]	alu_inst/alu_y_4_s7/F
21.634	0.004	tNET	FF	1	R29C29[2][B]	alu_inst/alu_y_4_s4/I1
22.096	0.462	tINS	FR	1	R29C29[2][B]	alu_inst/alu_y_4_s4/F
22.097	0.001	tNET	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/I1
22.646	0.549	tINS	RR	1	R29C29[3][A]	alu_inst/alu_y_4_s2/F
22.647	0.001	tNET	RR	1	R29C29[3][B]	alu_inst/alu_y_4_s0/I3
23.100	0.453	tINS	RF	6	R29C29[3][B]	alu_inst/alu_y_4_s0/F
24.522	1.421	tNET	FF	1	R32C26[1][B]	sequencer_inst/n27_s16/I3
25.092	0.570	tINS	FR	1	R32C26[1][B]	sequencer_inst/n27_s16/F
25.236	0.144	tNET	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/I2
25.785	0.549	tINS	RR	1	R32C26[1][A]	sequencer_inst/n27_s12/F
25.957	0.172	tNET	RR	1	R32C25[0][A]	sequencer_inst/n27_s10/I3
26.328	0.371	tINS	RF	1	R32C25[0][A]	sequencer_inst/n27_s10/F
27.012	0.684	tNET	FF	1	R27C24[0][B]	sequencer_inst/n27_s9/I3
27.474	0.462	tINS	FR	1	R27C24[0][B]	sequencer_inst/n27_s9/F
27.476	0.001	tNET	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/I3
28.046	0.570	tINS	RR	1	R27C24[2][A]	sequencer_inst/n27_s6/F
28.218	0.172	tNET	RR	1	R27C25[1][B]	sequencer_inst/n27_s4/I2
28.671	0.453	tINS	RF	5	R27C25[1][B]	sequencer_inst/n27_s4/F
29.697	1.026	tNET	FF	1	R34C28[3][A]	sequencer_inst/n27_s3/I2
30.150	0.453	tINS	FF	18	R34C28[3][A]	sequencer_inst/n27_s3/F
30.360	0.210	tNET	FF	1	R34C27[1][B]	sequencer_inst/n30_s0/I0
30.731	0.371	tINS	FF	1	R34C27[1][B]	sequencer_inst/n30_s0/F
30.731	0.000	tNET	FF	1	R34C27[1][B]	sequencer_inst/pc_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R34C27[1][B]	sequencer_inst/pc_5_s0/CLK
42.334	-0.035	tSu		1	R34C27[1][B]	sequencer_inst/pc_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	19
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 11.725, 46.158%; route: 11.417, 44.945%; tC2Q: 2.260, 8.897%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path19

Path Summary:

Slack	16.152
Data Arrival Time	26.182
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	register_file_inst/data_registers[0]_10_s1
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[10]
21.153	0.850	tNET	FF	1	R26C24[2][A]	alu_inst/alu_y_10_s4/I1
21.524	0.371	tINS	FF	1	R26C24[2][A]	alu_inst/alu_y_10_s4/F
21.938	0.413	tNET	FF	1	R29C24[3][A]	alu_inst/alu_y_10_s2/I1
22.487	0.549	tINS	FR	1	R29C24[3][A]	alu_inst/alu_y_10_s2/F
22.488	0.001	tNET	RR	1	R29C24[3][B]	alu_inst/alu_y_10_s0/I2
22.941	0.453	tINS	RF	6	R29C24[3][B]	alu_inst/alu_y_10_s0/F
25.612	2.671	tNET	FF	1	R20C31[1][A]	register_file_inst/n868_s0/I2
26.182	0.570	tINS	FR	1	R20C31[1][A]	register_file_inst/n868_s0/F
26.182	0.000	tNET	RR	1	R20C31[1][A]	register_file_inst/data_registers[0]_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R20C31[1][A]	register_file_inst/data_registers[0]_10_s1/CLK
42.334	-0.035	tSu		1	R20C31[1][A]	register_file_inst/data_registers[0]_10_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	11
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 8.034, 38.527%; route: 10.559, 50.635%; tC2Q: 2.260, 10.838%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path20

Path Summary:

Slack	16.196
Data Arrival Time	26.139
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	register_file_inst/data_registers[1]_10_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[10]
21.153	0.850	tNET	FF	1	R26C24[2][A]	alu_inst/alu_y_10_s4/I1
21.524	0.371	tINS	FF	1	R26C24[2][A]	alu_inst/alu_y_10_s4/F
21.938	0.413	tNET	FF	1	R29C24[3][A]	alu_inst/alu_y_10_s2/I1
22.487	0.549	tINS	FR	1	R29C24[3][A]	alu_inst/alu_y_10_s2/F
22.488	0.001	tNET	RR	1	R29C24[3][B]	alu_inst/alu_y_10_s0/I2
22.941	0.453	tINS	RF	6	R29C24[3][B]	alu_inst/alu_y_10_s0/F
26.139	3.198	tNET	FF	1	R21C31[2][A]	register_file_inst/data_registers[1]_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R21C31[2][A]	register_file_inst/data_registers[1]_10_s0/CLK
42.334	-0.035	tSu		1	R21C31[2][A]	register_file_inst/data_registers[1]_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	10
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 7.464, 35.868%; route: 11.085, 53.271%; tC2Q: 2.260, 10.860%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path21

Path Summary:

Slack	16.345
Data Arrival Time	25.989
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	register_file_inst/data_registers[2]_10_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[10]
21.153	0.850	tNET	FF	1	R26C24[2][A]	alu_inst/alu_y_10_s4/I1
21.524	0.371	tINS	FF	1	R26C24[2][A]	alu_inst/alu_y_10_s4/F
21.938	0.413	tNET	FF	1	R29C24[3][A]	alu_inst/alu_y_10_s2/I1
22.487	0.549	tINS	FR	1	R29C24[3][A]	alu_inst/alu_y_10_s2/F
22.488	0.001	tNET	RR	1	R29C24[3][B]	alu_inst/alu_y_10_s0/I2
22.941	0.453	tINS	RF	6	R29C24[3][B]	alu_inst/alu_y_10_s0/F
25.989	3.048	tNET	FF	1	R21C31[1][A]	register_file_inst/data_registers[2]_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R21C31[1][A]	register_file_inst/data_registers[2]_10_s0/CLK
42.334	-0.035	tSu		1	R21C31[1][A]	register_file_inst/data_registers[2]_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	10
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 7.464, 36.129%; route: 10.936, 52.932%; tC2Q: 2.260, 10.939%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path22

Path Summary:

Slack	16.761
Data Arrival Time	25.573
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	register_file_inst/data_registers[0]_24_s1
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[24]
20.716	0.413	tNET	FF	1	R22C24[3][B]	alu_inst/alu_y_24_s11/I1
21.271	0.555	tINS	FF	1	R22C24[3][B]	alu_inst/alu_y_24_s11/F
21.927	0.656	tNET	FF	1	R27C24[3][B]	alu_inst/alu_y_24_s3/I2
22.298	0.371	tINS	FF	1	R27C24[3][B]	alu_inst/alu_y_24_s3/F
22.954	0.656	tNET	FF	1	R31C23[1][A]	alu_inst/alu_y_24_s/I3
23.509	0.555	tINS	FF	4	R31C23[1][A]	alu_inst/alu_y_24_s/F
25.111	1.602	tNET	FF	1	R30C35[0][A]	register_file_inst/n854_s0/I2
25.573	0.462	tINS	FR	1	R30C35[0][A]	register_file_inst/n854_s0/F
25.573	0.000	tNET	RR	1	R30C35[0][A]	register_file_inst/data_registers[0]_24_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R30C35[0][A]	register_file_inst/data_registers[0]_24_s1/CLK
42.334	-0.035	tSu		1	R30C35[0][A]	register_file_inst/data_registers[0]_24_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	11
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 8.034, 39.686%; route: 9.950, 49.150%; tC2Q: 2.260, 11.164%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path23

Path Summary:

Slack	16.852
Data Arrival Time	25.482
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	register_file_inst/data_registers[2]_24_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[24]
20.716	0.413	tNET	FF	1	R22C24[3][B]	alu_inst/alu_y_24_s11/I1
21.271	0.555	tINS	FF	1	R22C24[3][B]	alu_inst/alu_y_24_s11/F
21.927	0.656	tNET	FF	1	R27C24[3][B]	alu_inst/alu_y_24_s3/I2
22.298	0.371	tINS	FF	1	R27C24[3][B]	alu_inst/alu_y_24_s3/F
22.954	0.656	tNET	FF	1	R31C23[1][A]	alu_inst/alu_y_24_s/I3
23.509	0.555	tINS	FF	4	R31C23[1][A]	alu_inst/alu_y_24_s/F
25.482	1.973	tNET	FF	1	R30C35[2][A]	register_file_inst/data_registers[2]_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R30C35[2][A]	register_file_inst/data_registers[2]_24_s0/CLK
42.334	-0.035	tSu		1	R30C35[2][A]	register_file_inst/data_registers[2]_24_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	10
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 7.572, 37.573%; route: 10.321, 51.213%; tC2Q: 2.260, 11.214%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path24

Path Summary:

Slack	16.921
Data Arrival Time	25.413
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	register_file_inst/data_registers[2]_7_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[7]
20.958	0.655	tNET	FF	1	R20C24[1][A]	alu_inst/alu_y_7_s8/I1
21.411	0.453	tINS	FF	1	R20C24[1][A]	alu_inst/alu_y_7_s8/F
21.901	0.490	tNET	FF	1	R24C24[3][B]	alu_inst/alu_y_7_s4/I2
22.363	0.462	tINS	FR	1	R24C24[3][B]	alu_inst/alu_y_7_s4/F
22.535	0.172	tNET	RR	1	R24C25[3][B]	alu_inst/alu_y_7_s1/I2
22.997	0.462	tINS	RR	1	R24C25[3][B]	alu_inst/alu_y_7_s1/F
22.999	0.001	tNET	RR	1	R24C25[2][B]	alu_inst/alu_y_7_s0/I0
23.516	0.517	tINS	RF	6	R24C25[2][B]	alu_inst/alu_y_7_s0/F
25.413	1.897	tNET	FF	1	R30C35[1][B]	register_file_inst/data_registers[2]_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R30C35[1][B]	register_file_inst/data_registers[2]_7_s0/CLK
42.334	-0.035	tSu		1	R30C35[1][B]	register_file_inst/data_registers[2]_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	11
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 7.985, 39.758%; route: 9.839, 48.989%; tC2Q: 2.260, 11.253%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Path25

Path Summary:

Slack	16.921
Data Arrival Time	25.413
Data Required Time	42.334
From	microcode_rom_microcode_rom_0_0_s
To	register_file_inst/data_registers[1]_7_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
2.088	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
5.329	3.241	tNET	RR	32	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/CLK
7.589	2.260	tC2Q	RF	73	BSRAM_R46[9]	microcode_rom_microcode_rom_0_0_s/DO[11]
8.569	0.980	tNET	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/I2
9.086	0.517	tINS	FF	1	R32C37[3][B]	register_file_inst/addr_registers[0]_ER_CL_s44/F
9.499	0.413	tNET	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/I1
9.870	0.371	tINS	FF	1	R31C36[3][A]	register_file_inst/addr_registers[0]_ER_CL_s41/F
10.283	0.413	tNET	FF	1	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/I0
10.654	0.371	tINS	FF	24	R31C33[2][B]	register_file_inst/addr_registers[0]_ER_init_s20/F
11.842	1.188	tNET	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/I0
12.397	0.555	tINS	FF	1	R30C30[3][A]	register_file_inst/alu_a_4_s2/F
12.810	0.413	tNET	FF	1	R30C33[0][B]	register_file_inst/alu_a_4_s/I2
13.327	0.517	tINS	FF	11	R30C33[0][B]	register_file_inst/alu_a_4_s/F
16.543	3.216	tNET	FF	72	DSP_R19[2]	alu_inst/mult_172_s1/A[4]
20.303	3.760	tINS	FF	1	DSP_R19[2]	alu_inst/mult_172_s1/DOUT[7]
20.958	0.655	tNET	FF	1	R20C24[1][A]	alu_inst/alu_y_7_s8/I1
21.411	0.453	tINS	FF	1	R20C24[1][A]	alu_inst/alu_y_7_s8/F
21.901	0.490	tNET	FF	1	R24C24[3][B]	alu_inst/alu_y_7_s4/I2
22.363	0.462	tINS	FR	1	R24C24[3][B]	alu_inst/alu_y_7_s4/F
22.535	0.172	tNET	RR	1	R24C25[3][B]	alu_inst/alu_y_7_s1/I2
22.997	0.462	tINS	RR	1	R24C25[3][B]	alu_inst/alu_y_7_s1/F
22.999	0.001	tNET	RR	1	R24C25[2][B]	alu_inst/alu_y_7_s0/I0
23.516	0.517	tINS	RF	6	R24C25[2][B]	alu_inst/alu_y_7_s0/F
25.413	1.897	tNET	FF	1	R31C35[1][A]	register_file_inst/data_registers[1]_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.040	37.040					active clock edge time
37.040	0.000					i_clk
37.040	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
39.128	2.088	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
42.369	3.241	tNET	RR	1	R31C35[1][A]	register_file_inst/data_registers[1]_7_s0/CLK
42.334	-0.035	tSu		1	R31C35[1][A]	register_file_inst/data_registers[1]_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	37.040
Logic Level	11
Arrival Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%
Arrival Data Path Delay	cell: 7.985, 39.758%; route: 9.839, 48.989%; tC2Q: 2.260, 11.253%
Required Clock Path Delay	cell: 2.088, 39.180%; route: 3.241, 60.820%

Hold Analysis Report

Report Command:report_timing -hold -from_clock [get_clocks {i_clk}] -to_clock [get_clocks {i_clk}] -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.327
Data Arrival Time	4.159
Data Required Time	3.832
From	register_file_inst/data_registers[0]_1_s1
To	sram_srom_inst/sram0_sram0_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R24C31[0][A]	register_file_inst/data_registers[0]_1_s1/CLK
3.785	0.202	tC2Q	RR	6	R24C31[0][A]	register_file_inst/data_registers[0]_1_s1/Q
4.159	0.374	tNET	RR	1	BSRAM_R28[8]	sram_srom_inst/sram0_sram0_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[8]	sram_srom_inst/sram0_sram0_0_0_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[8]	sram_srom_inst/sram0_sram0_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.374, 64.958%; tC2Q: 0.202, 35.042%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path2

Path Summary:

Slack	0.341
Data Arrival Time	4.173
Data Required Time	3.832
From	register_file_inst/data_registers[0]_0_s1
To	sram_srom_inst/sram0_sram0_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R23C32[1][A]	register_file_inst/data_registers[0]_0_s1/CLK
3.785	0.202	tC2Q	RR	6	R23C32[1][A]	register_file_inst/data_registers[0]_0_s1/Q
4.173	0.388	tNET	RR	1	BSRAM_R28[8]	sram_srom_inst/sram0_sram0_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[8]	sram_srom_inst/sram0_sram0_0_0_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[8]	sram_srom_inst/sram0_sram0_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 65.750%; tC2Q: 0.202, 34.250%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path3

Path Summary:

Slack	0.427
Data Arrival Time	4.021
Data Required Time	3.594
From	sequencer_inst/pc_1_s0
To	sequencer_inst/pc_1_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R33C28[1][A]	sequencer_inst/pc_1_s0/CLK
3.785	0.202	tC2Q	RR	6	R33C28[1][A]	sequencer_inst/pc_1_s0/Q
3.789	0.004	tNET	RR	1	R33C28[1][A]	sequencer_inst/n34_s0/I2
4.021	0.232	tINS	RF	1	R33C28[1][A]	sequencer_inst/n34_s0/F
4.021	0.000	tNET	FF	1	R33C28[1][A]	sequencer_inst/pc_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R33C28[1][A]	sequencer_inst/pc_1_s0/CLK
3.594	0.011	tHld		1	R33C28[1][A]	sequencer_inst/pc_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path4

Path Summary:

Slack	0.427
Data Arrival Time	4.021
Data Required Time	3.594
From	sequencer_inst/pc_6_s0
To	sequencer_inst/pc_6_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R34C27[1][A]	sequencer_inst/pc_6_s0/CLK
3.785	0.202	tC2Q	RR	4	R34C27[1][A]	sequencer_inst/pc_6_s0/Q
3.789	0.004	tNET	RR	1	R34C27[1][A]	sequencer_inst/n29_s0/I2
4.021	0.232	tINS	RF	1	R34C27[1][A]	sequencer_inst/n29_s0/F
4.021	0.000	tNET	FF	1	R34C27[1][A]	sequencer_inst/pc_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R34C27[1][A]	sequencer_inst/pc_6_s0/CLK
3.594	0.011	tHld		1	R34C27[1][A]	sequencer_inst/pc_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path5

Path Summary:

Slack	0.428
Data Arrival Time	4.022
Data Required Time	3.594
From	sequencer_inst/pc_7_s0
To	sequencer_inst/pc_7_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R34C27[0][A]	sequencer_inst/pc_7_s0/CLK
3.785	0.202	tC2Q	RR	4	R34C27[0][A]	sequencer_inst/pc_7_s0/Q
3.790	0.005	tNET	RR	1	R34C27[0][A]	sequencer_inst/n28_s0/I1
4.022	0.232	tINS	RF	1	R34C27[0][A]	sequencer_inst/n28_s0/F
4.022	0.000	tNET	FF	1	R34C27[0][A]	sequencer_inst/pc_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R34C27[0][A]	sequencer_inst/pc_7_s0/CLK
3.594	0.011	tHld		1	R34C27[0][A]	sequencer_inst/pc_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path6

Path Summary:

Slack	0.429
Data Arrival Time	4.023
Data Required Time	3.594
From	sequencer_inst/pc_3_s0
To	sequencer_inst/pc_3_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R34C26[0][A]	sequencer_inst/pc_3_s0/CLK
3.785	0.202	tC2Q	RR	6	R34C26[0][A]	sequencer_inst/pc_3_s0/Q
3.791	0.006	tNET	RR	1	R34C26[0][A]	sequencer_inst/n32_s0/I1
4.023	0.232	tINS	RF	1	R34C26[0][A]	sequencer_inst/n32_s0/F
4.023	0.000	tNET	FF	1	R34C26[0][A]	sequencer_inst/pc_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R34C26[0][A]	sequencer_inst/pc_3_s0/CLK
3.594	0.011	tHld		1	R34C26[0][A]	sequencer_inst/pc_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path7

Path Summary:

Slack	0.485
Data Arrival Time	4.079
Data Required Time	3.594
From	sequencer_inst/pc_0_s2
To	sequencer_inst/pc_0_s2
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R33C28[2][A]	sequencer_inst/pc_0_s2/CLK
3.785	0.202	tC2Q	RR	8	R33C28[2][A]	sequencer_inst/pc_0_s2/Q
3.789	0.004	tNET	RR	1	R33C28[2][A]	sequencer_inst/n35_s8/I1
4.079	0.290	tINS	RF	1	R33C28[2][A]	sequencer_inst/n35_s8/F
4.079	0.000	tNET	FF	1	R33C28[2][A]	sequencer_inst/pc_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R33C28[2][A]	sequencer_inst/pc_0_s2/CLK
3.594	0.011	tHld		1	R33C28[2][A]	sequencer_inst/pc_0_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.290, 58.507%; route: 0.004, 0.740%; tC2Q: 0.202, 40.753%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path8

Path Summary:

Slack	0.485
Data Arrival Time	4.079
Data Required Time	3.594
From	sequencer_inst/pc_2_s0
To	sequencer_inst/pc_2_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R33C27[2][A]	sequencer_inst/pc_2_s0/CLK
3.785	0.202	tC2Q	RR	4	R33C27[2][A]	sequencer_inst/pc_2_s0/Q
3.789	0.004	tNET	RR	1	R33C27[2][A]	sequencer_inst/n33_s0/I1
4.079	0.290	tINS	RF	1	R33C27[2][A]	sequencer_inst/n33_s0/F
4.079	0.000	tNET	FF	1	R33C27[2][A]	sequencer_inst/pc_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R33C27[2][A]	sequencer_inst/pc_2_s0/CLK
3.594	0.011	tHld		1	R33C27[2][A]	sequencer_inst/pc_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.290, 58.507%; route: 0.004, 0.740%; tC2Q: 0.202, 40.753%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path9

Path Summary:

Slack	0.514
Data Arrival Time	4.346
Data Required Time	3.832
From	register_file_inst/data_registers[0]_7_s1
To	sram_srom_inst/sram0_sram0_0_1_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R25C34[0][A]	register_file_inst/data_registers[0]_7_s1/CLK
3.785	0.202	tC2Q	RR	21	R25C34[0][A]	register_file_inst/data_registers[0]_7_s1/Q
4.346	0.561	tNET	RR	1	BSRAM_R10[10]	sram_srom_inst/sram0_sram0_0_1_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R10[10]	sram_srom_inst/sram0_sram0_0_1_s/CLK
3.832	0.249	tHld		1	BSRAM_R10[10]	sram_srom_inst/sram0_sram0_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.561, 73.535%; tC2Q: 0.202, 26.465%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path10

Path Summary:

Slack	0.542
Data Arrival Time	4.136
Data Required Time	3.594
From	sequencer_inst/pc_4_s0
To	sequencer_inst/pc_4_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R33C26[1][B]	sequencer_inst/pc_4_s0/CLK
3.784	0.201	tC2Q	RF	4	R33C26[1][B]	sequencer_inst/pc_4_s0/Q
3.904	0.120	tNET	FF	1	R33C26[1][B]	sequencer_inst/n31_s0/I2
4.136	0.232	tINS	FF	1	R33C26[1][B]	sequencer_inst/n31_s0/F
4.136	0.000	tNET	FF	1	R33C26[1][B]	sequencer_inst/pc_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R33C26[1][B]	sequencer_inst/pc_4_s0/CLK
3.594	0.011	tHld		1	R33C26[1][B]	sequencer_inst/pc_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path11

Path Summary:

Slack	0.546
Data Arrival Time	4.140
Data Required Time	3.594
From	sequencer_inst/pc_8_s0
To	sequencer_inst/pc_8_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R33C27[1][B]	sequencer_inst/pc_8_s0/CLK
3.784	0.201	tC2Q	RF	2	R33C27[1][B]	sequencer_inst/pc_8_s0/Q
3.908	0.124	tNET	FF	1	R33C27[1][B]	sequencer_inst/n27_s0/I2
4.140	0.232	tINS	FF	1	R33C27[1][B]	sequencer_inst/n27_s0/F
4.140	0.000	tNET	FF	1	R33C27[1][B]	sequencer_inst/pc_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R33C27[1][B]	sequencer_inst/pc_8_s0/CLK
3.594	0.011	tHld		1	R33C27[1][B]	sequencer_inst/pc_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path12

Path Summary:

Slack	0.558
Data Arrival Time	4.390
Data Required Time	3.832
From	register_file_inst/data_registers[0]_2_s1
To	sram_srom_inst/sram1_sram1_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R31C35[0][B]	register_file_inst/data_registers[0]_2_s1/CLK
3.785	0.202	tC2Q	RR	21	R31C35[0][B]	register_file_inst/data_registers[0]_2_s1/Q
4.036	0.251	tNET	RR	1	R27C35[2][A]	sram_srom_inst/wdata1_2_s0/I1
4.268	0.232	tINS	RF	1	R27C35[2][A]	sram_srom_inst/wdata1_2_s0/F
4.390	0.122	tNET	FF	1	BSRAM_R28[9]	sram_srom_inst/sram1_sram1_0_0_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[9]	sram_srom_inst/sram1_sram1_0_0_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[9]	sram_srom_inst/sram1_sram1_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.232, 28.736%; route: 0.373, 46.244%; tC2Q: 0.202, 25.020%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path13

Path Summary:

Slack	0.560
Data Arrival Time	4.154
Data Required Time	3.594
From	sequencer_inst/pc_5_s0
To	sequencer_inst/pc_5_s0
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R34C27[1][B]	sequencer_inst/pc_5_s0/CLK
3.785	0.202	tC2Q	RR	6	R34C27[1][B]	sequencer_inst/pc_5_s0/Q
3.790	0.005	tNET	RR	1	R34C27[1][B]	sequencer_inst/n30_s0/I1
4.154	0.364	tINS	RF	1	R34C27[1][B]	sequencer_inst/n30_s0/F
4.154	0.000	tNET	FF	1	R34C27[1][B]	sequencer_inst/pc_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R34C27[1][B]	sequencer_inst/pc_5_s0/CLK
3.594	0.011	tHld		1	R34C27[1][B]	sequencer_inst/pc_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.364, 63.760%; route: 0.005, 0.856%; tC2Q: 0.202, 35.383%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path14

Path Summary:

Slack	0.571
Data Arrival Time	4.403
Data Required Time	3.832
From	register_file_inst/data_registers[0]_2_s1
To	sram_srom_inst/sram0_sram0_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R31C35[0][B]	register_file_inst/data_registers[0]_2_s1/CLK
3.785	0.202	tC2Q	RR	21	R31C35[0][B]	register_file_inst/data_registers[0]_2_s1/Q
4.403	0.618	tNET	RR	1	BSRAM_R28[8]	sram_srom_inst/sram0_sram0_0_0_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[8]	sram_srom_inst/sram0_sram0_0_0_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[8]	sram_srom_inst/sram0_sram0_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.618, 75.372%; tC2Q: 0.202, 24.628%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path15

Path Summary:

Slack	0.612
Data Arrival Time	4.444
Data Required Time	3.832
From	register_file_inst/data_registers[0]_3_s1
To	sram_srom_inst/sram0_sram0_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R21C33[0][B]	register_file_inst/data_registers[0]_3_s1/CLK
3.785	0.202	tC2Q	RR	19	R21C33[0][B]	register_file_inst/data_registers[0]_3_s1/Q
4.444	0.659	tNET	RR	1	BSRAM_R28[8]	sram_srom_inst/sram0_sram0_0_0_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[8]	sram_srom_inst/sram0_sram0_0_0_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[8]	sram_srom_inst/sram0_sram0_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.536%; tC2Q: 0.202, 23.464%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path16

Path Summary:

Slack	0.651
Data Arrival Time	4.483
Data Required Time	3.832
From	register_file_inst/data_registers[0]_4_s1
To	sram_srom_inst/sram0_sram0_0_1_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R26C30[2][A]	register_file_inst/data_registers[0]_4_s1/CLK
3.785	0.202	tC2Q	RR	23	R26C30[2][A]	register_file_inst/data_registers[0]_4_s1/Q
4.483	0.698	tNET	RR	1	BSRAM_R10[10]	sram_srom_inst/sram0_sram0_0_1_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R10[10]	sram_srom_inst/sram0_sram0_0_1_s/CLK
3.832	0.249	tHld		1	BSRAM_R10[10]	sram_srom_inst/sram0_sram0_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.698, 77.560%; tC2Q: 0.202, 22.440%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path17

Path Summary:

Slack	0.721
Data Arrival Time	4.553
Data Required Time	3.832
From	register_file_inst/data_registers[0]_8_s1
To	sram_srom_inst/sram1_sram1_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R22C35[1][B]	register_file_inst/data_registers[0]_8_s1/CLK
3.785	0.202	tC2Q	RR	4	R22C35[1][B]	register_file_inst/data_registers[0]_8_s1/Q
4.199	0.414	tNET	RR	1	R29C35[1][B]	sram_srom_inst/wdata1_0_s0/I0
4.431	0.232	tINS	RF	1	R29C35[1][B]	sram_srom_inst/wdata1_0_s0/F
4.553	0.122	tNET	FF	1	BSRAM_R28[9]	sram_srom_inst/sram1_sram1_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[9]	sram_srom_inst/sram1_sram1_0_0_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[9]	sram_srom_inst/sram1_sram1_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.232, 23.919%; route: 0.536, 55.255%; tC2Q: 0.202, 20.826%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path18

Path Summary:

Slack	0.837
Data Arrival Time	4.669
Data Required Time	3.832
From	register_file_inst/data_registers[0]_1_s1
To	sram_srom_inst/sram1_sram1_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R24C31[0][A]	register_file_inst/data_registers[0]_1_s1/CLK
3.785	0.202	tC2Q	RR	6	R24C31[0][A]	register_file_inst/data_registers[0]_1_s1/Q
4.059	0.274	tNET	RR	1	R26C35[2][A]	sram_srom_inst/wdata1_1_s0/I1
4.403	0.344	tINS	RF	1	R26C35[2][A]	sram_srom_inst/wdata1_1_s0/F
4.669	0.266	tNET	FF	1	BSRAM_R28[9]	sram_srom_inst/sram1_sram1_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[9]	sram_srom_inst/sram1_sram1_0_0_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[9]	sram_srom_inst/sram1_sram1_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.344, 31.680%; route: 0.540, 49.717%; tC2Q: 0.202, 18.603%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path19

Path Summary:

Slack	0.846
Data Arrival Time	4.678
Data Required Time	3.832
From	register_file_inst/data_registers[0]_1_s1
To	sram_srom_inst/sram2_sram2_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R24C31[0][A]	register_file_inst/data_registers[0]_1_s1/CLK
3.785	0.202	tC2Q	RR	6	R24C31[0][A]	register_file_inst/data_registers[0]_1_s1/Q
4.320	0.535	tNET	RR	1	R27C38[0][A]	sram_srom_inst/wdata2_1_s1/I1
4.555	0.235	tINS	RR	1	R27C38[0][A]	sram_srom_inst/wdata2_1_s1/F
4.678	0.123	tNET	RR	1	BSRAM_R28[10]	sram_srom_inst/sram2_sram2_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[10]	sram_srom_inst/sram2_sram2_0_0_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[10]	sram_srom_inst/sram2_sram2_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.235, 21.454%; route: 0.658, 60.105%; tC2Q: 0.202, 18.441%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path20

Path Summary:

Slack	0.848
Data Arrival Time	4.680
Data Required Time	3.832
From	register_file_inst/data_registers[0]_16_s1
To	sram_srom_inst/sram2_sram2_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R25C33[2][A]	register_file_inst/data_registers[0]_16_s1/CLK
3.785	0.202	tC2Q	RR	3	R25C33[2][A]	register_file_inst/data_registers[0]_16_s1/Q
4.196	0.411	tNET	RR	1	R26C38[3][A]	sram_srom_inst/wdata2_0_s1/I0
4.431	0.235	tINS	RR	1	R26C38[3][A]	sram_srom_inst/wdata2_0_s1/F
4.680	0.249	tNET	RR	1	BSRAM_R28[10]	sram_srom_inst/sram2_sram2_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[10]	sram_srom_inst/sram2_sram2_0_0_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[10]	sram_srom_inst/sram2_sram2_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.235, 21.420%; route: 0.660, 60.168%; tC2Q: 0.202, 18.412%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path21

Path Summary:

Slack	0.851
Data Arrival Time	4.683
Data Required Time	3.832
From	register_file_inst/data_registers[0]_20_s1
To	sram_srom_inst/sram2_sram2_0_1_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R27C36[1][B]	register_file_inst/data_registers[0]_20_s1/CLK
3.785	0.202	tC2Q	RR	3	R27C36[1][B]	register_file_inst/data_registers[0]_20_s1/Q
3.909	0.124	tNET	RR	1	R27C38[1][B]	sram_srom_inst/wdata2_4_s1/I0
4.300	0.391	tINS	RR	1	R27C38[1][B]	sram_srom_inst/wdata2_4_s1/F
4.683	0.382	tNET	RR	1	BSRAM_R28[11]	sram_srom_inst/sram2_sram2_0_1_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[11]	sram_srom_inst/sram2_sram2_0_1_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[11]	sram_srom_inst/sram2_sram2_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.391, 35.549%; route: 0.507, 46.085%; tC2Q: 0.202, 18.366%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path22

Path Summary:

Slack	0.863
Data Arrival Time	4.695
Data Required Time	3.832
From	register_file_inst/data_registers[0]_2_s1
To	sram_srom_inst/sram3_sram3_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R31C35[0][B]	register_file_inst/data_registers[0]_2_s1/CLK
3.785	0.202	tC2Q	RR	21	R31C35[0][B]	register_file_inst/data_registers[0]_2_s1/Q
4.036	0.251	tNET	RR	1	R27C35[3][A]	sram_srom_inst/wdata3_2_s0/I0
4.268	0.232	tINS	RF	1	R27C35[3][A]	sram_srom_inst/wdata3_2_s0/F
4.695	0.427	tNET	FF	1	BSRAM_R28[12]	sram_srom_inst/sram3_sram3_0_0_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[12]	sram_srom_inst/sram3_sram3_0_0_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[12]	sram_srom_inst/sram3_sram3_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.232, 20.855%; route: 0.678, 60.987%; tC2Q: 0.202, 18.158%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path23

Path Summary:

Slack	0.890
Data Arrival Time	4.722
Data Required Time	3.832
From	register_file_inst/data_registers[0]_19_s1
To	sram_srom_inst/sram2_sram2_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R21C34[0][A]	register_file_inst/data_registers[0]_19_s1/CLK
3.785	0.202	tC2Q	RR	3	R21C34[0][A]	register_file_inst/data_registers[0]_19_s1/Q
4.208	0.423	tNET	RR	1	R27C38[1][A]	sram_srom_inst/wdata2_3_s1/I0
4.599	0.391	tINS	RR	1	R27C38[1][A]	sram_srom_inst/wdata2_3_s1/F
4.722	0.123	tNET	RR	1	BSRAM_R28[10]	sram_srom_inst/sram2_sram2_0_0_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[10]	sram_srom_inst/sram2_sram2_0_0_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[10]	sram_srom_inst/sram2_sram2_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.391, 34.322%; route: 0.546, 47.947%; tC2Q: 0.202, 17.731%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path24

Path Summary:

Slack	0.891
Data Arrival Time	4.485
Data Required Time	3.594
From	sram_srom_inst/mdata_6_s0
To	register_file_inst/data_registers[0]_6_s1
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R30C36[0][A]	sram_srom_inst/mdata_6_s0/CLK
3.784	0.201	tC2Q	RF	1	R30C36[0][A]	sram_srom_inst/mdata_6_s0/Q
3.906	0.122	tNET	FF	1	R31C36[2][B]	register_file_inst/n872_s2/I0
4.138	0.232	tINS	FF	1	R31C36[2][B]	register_file_inst/n872_s2/F
4.141	0.004	tNET	FF	1	R31C36[1][A]	register_file_inst/n872_s0/I1
4.485	0.344	tINS	FF	1	R31C36[1][A]	register_file_inst/n872_s0/F
4.485	0.000	tNET	FF	1	R31C36[1][A]	register_file_inst/data_registers[0]_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R31C36[1][A]	register_file_inst/data_registers[0]_6_s1/CLK
3.594	0.011	tHld		1	R31C36[1][A]	register_file_inst/data_registers[0]_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.576, 63.830%; route: 0.125, 13.896%; tC2Q: 0.201, 22.274%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Path25

Path Summary:

Slack	0.896
Data Arrival Time	4.728
Data Required Time	3.832
From	register_file_inst/data_registers[0]_11_s1
To	sram_srom_inst/sram1_sram1_0_0_s
Launch Clk	i_clk:[R]
Latch Clk	i_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	R22C35[1][A]	register_file_inst/data_registers[0]_11_s1/CLK
3.785	0.202	tC2Q	RR	4	R22C35[1][A]	register_file_inst/data_registers[0]_11_s1/Q
4.172	0.387	tNET	RR	1	R27C35[0][B]	sram_srom_inst/wdata1_3_s0/I0
4.462	0.290	tINS	RF	1	R27C35[0][B]	sram_srom_inst/wdata1_3_s0/F
4.728	0.266	tNET	FF	1	BSRAM_R28[9]	sram_srom_inst/sram1_sram1_0_0_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					i_clk
0.000	0.000	tCL	RR	1	IOL7[A]	i_clk_ibuf/I
1.392	1.392	tINS	RR	163	IOL7[A]	i_clk_ibuf/O
3.583	2.191	tNET	RR	1	BSRAM_R28[9]	sram_srom_inst/sram1_sram1_0_0_s/CLK
3.832	0.249	tHld		1	BSRAM_R28[9]	sram_srom_inst/sram1_sram1_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%
Arrival Data Path Delay	cell: 0.290, 25.333%; route: 0.653, 57.022%; tC2Q: 0.202, 17.645%
Required Clock Path Delay	cell: 1.392, 38.851%; route: 2.191, 61.149%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	15.323
Actual Width:	16.323
Required Width:	1.000
Type:	Low Pulse Width
Clock:	i_clk
Objects:	strobe_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
18.518	0.000			active clock edge time
18.518	0.000			i_clk
18.518	0.000	tCL	FF	i_clk_ibuf/I
20.832	2.314	tINS	FF	i_clk_ibuf/O
24.300	3.468	tNET	FF	strobe_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
37.040	0.000			active clock edge time
37.040	0.000			i_clk
37.040	0.000	tCL	RR	i_clk_ibuf/I
38.432	1.392	tINS	RR	i_clk_ibuf/O
40.623	2.191	tNET	RR	strobe_s0/CLK

MPW2

MPW Summary:

Slack:	15.323
Actual Width:	16.323
Required Width:	1.000
Type:	Low Pulse Width
Clock:	i_clk
Objects:	o_led_5_s2

Late clock Path:

AT	DELAY	TYPE	RF	NODE
18.518	0.000			active clock edge time
18.518	0.000			i_clk
18.518	0.000	tCL	FF	i_clk_ibuf/I
20.832	2.314	tINS	FF	i_clk_ibuf/O
24.300	3.468	tNET	FF	o_led_5_s2/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
37.040	0.000			active clock edge time
37.040	0.000			i_clk
37.040	0.000	tCL	RR	i_clk_ibuf/I
38.432	1.392	tINS	RR	i_clk_ibuf/O
40.623	2.191	tNET	RR	o_led_5_s2/CLK

MPW3

MPW Summary:

Slack:	15.323
Actual Width:	16.323
Required Width:	1.000
Type:	Low Pulse Width
Clock:	i_clk
Objects:	o_led_3_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
18.518	0.000			active clock edge time
18.518	0.000			i_clk
18.518	0.000	tCL	FF	i_clk_ibuf/I
20.832	2.314	tINS	FF	i_clk_ibuf/O
24.300	3.468	tNET	FF	o_led_3_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
37.040	0.000			active clock edge time
37.040	0.000			i_clk
37.040	0.000	tCL	RR	i_clk_ibuf/I
38.432	1.392	tINS	RR	i_clk_ibuf/O
40.623	2.191	tNET	RR	o_led_3_s1/CLK

MPW4

MPW Summary:

Slack:	15.323
Actual Width:	16.323
Required Width:	1.000
Type:	Low Pulse Width
Clock:	i_clk
Objects:	microcode_rom_microcode_rom_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
18.518	0.000			active clock edge time
18.518	0.000			i_clk
18.518	0.000	tCL	FF	i_clk_ibuf/I
20.832	2.314	tINS	FF	i_clk_ibuf/O
24.300	3.468	tNET	FF	microcode_rom_microcode_rom_0_0_s/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
37.040	0.000			active clock edge time
37.040	0.000			i_clk
37.040	0.000	tCL	RR	i_clk_ibuf/I
38.432	1.392	tINS	RR	i_clk_ibuf/O
40.623	2.191	tNET	RR	microcode_rom_microcode_rom_0_0_s/CLK

MPW5

MPW Summary:

Slack:	15.323
Actual Width:	16.323
Required Width:	1.000
Type:	Low Pulse Width
Clock:	i_clk
Objects:	register_file_inst/data_registers[1]_24_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
18.518	0.000			active clock edge time
18.518	0.000			i_clk
18.518	0.000	tCL	FF	i_clk_ibuf/I
20.832	2.314	tINS	FF	i_clk_ibuf/O
24.300	3.468	tNET	FF	register_file_inst/data_registers[1]_24_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
37.040	0.000			active clock edge time
37.040	0.000			i_clk
37.040	0.000	tCL	RR	i_clk_ibuf/I
38.432	1.392	tINS	RR	i_clk_ibuf/O
40.623	2.191	tNET	RR	register_file_inst/data_registers[1]_24_s0/CLK

MPW6

MPW Summary:

Slack:	15.323
Actual Width:	16.323
Required Width:	1.000
Type:	Low Pulse Width
Clock:	i_clk
Objects:	register_file_inst/data_registers[1]_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
18.518	0.000			active clock edge time
18.518	0.000			i_clk
18.518	0.000	tCL	FF	i_clk_ibuf/I
20.832	2.314	tINS	FF	i_clk_ibuf/O
24.300	3.468	tNET	FF	register_file_inst/data_registers[1]_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
37.040	0.000			active clock edge time
37.040	0.000			i_clk
37.040	0.000	tCL	RR	i_clk_ibuf/I
38.432	1.392	tINS	RR	i_clk_ibuf/O
40.623	2.191	tNET	RR	register_file_inst/data_registers[1]_8_s0/CLK

MPW7

MPW Summary:

Slack:	15.323
Actual Width:	16.323
Required Width:	1.000
Type:	Low Pulse Width
Clock:	i_clk
Objects:	register_file_inst/data_registers[2]_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
18.518	0.000			active clock edge time
18.518	0.000			i_clk
18.518	0.000	tCL	FF	i_clk_ibuf/I
20.832	2.314	tINS	FF	i_clk_ibuf/O
24.300	3.468	tNET	FF	register_file_inst/data_registers[2]_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
37.040	0.000			active clock edge time
37.040	0.000			i_clk
37.040	0.000	tCL	RR	i_clk_ibuf/I
38.432	1.392	tINS	RR	i_clk_ibuf/O
40.623	2.191	tNET	RR	register_file_inst/data_registers[2]_8_s0/CLK

MPW8

MPW Summary:

Slack:	15.323
Actual Width:	16.323
Required Width:	1.000
Type:	Low Pulse Width
Clock:	i_clk
Objects:	sram_srom_inst/mdata_21_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
18.518	0.000			active clock edge time
18.518	0.000			i_clk
18.518	0.000	tCL	FF	i_clk_ibuf/I
20.832	2.314	tINS	FF	i_clk_ibuf/O
24.300	3.468	tNET	FF	sram_srom_inst/mdata_21_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
37.040	0.000			active clock edge time
37.040	0.000			i_clk
37.040	0.000	tCL	RR	i_clk_ibuf/I
38.432	1.392	tINS	RR	i_clk_ibuf/O
40.623	2.191	tNET	RR	sram_srom_inst/mdata_21_s0/CLK

MPW9

MPW Summary:

Slack:	15.323
Actual Width:	16.323
Required Width:	1.000
Type:	Low Pulse Width
Clock:	i_clk
Objects:	sram_srom_inst/mdata_20_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
18.518	0.000			active clock edge time
18.518	0.000			i_clk
18.518	0.000	tCL	FF	i_clk_ibuf/I
20.832	2.314	tINS	FF	i_clk_ibuf/O
24.300	3.468	tNET	FF	sram_srom_inst/mdata_20_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
37.040	0.000			active clock edge time
37.040	0.000			i_clk
37.040	0.000	tCL	RR	i_clk_ibuf/I
38.432	1.392	tINS	RR	i_clk_ibuf/O
40.623	2.191	tNET	RR	sram_srom_inst/mdata_20_s0/CLK

MPW10

MPW Summary:

Slack:	15.323
Actual Width:	16.323
Required Width:	1.000
Type:	Low Pulse Width
Clock:	i_clk
Objects:	register_file_inst/data_registers[2]_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
18.518	0.000			active clock edge time
18.518	0.000			i_clk
18.518	0.000	tCL	FF	i_clk_ibuf/I
20.832	2.314	tINS	FF	i_clk_ibuf/O
24.300	3.468	tNET	FF	register_file_inst/data_registers[2]_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
37.040	0.000			active clock edge time
37.040	0.000			i_clk
37.040	0.000	tCL	RR	i_clk_ibuf/I
38.432	1.392	tINS	RR	i_clk_ibuf/O
40.623	2.191	tNET	RR	register_file_inst/data_registers[2]_7_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
163	i_clk_d	9.949	3.468
122	alu_op[0]_1_2	15.234	1.669
92	alu_inst/o_y_0_37	14.591	2.429
87	rf_rs2_data[3]	14.423	2.029
73	uinst[12]	9.949	1.174
71	rf_rs2_data[1]	13.755	1.931
69	rf_rs2_data[0]	14.274	2.505
61	uinst[10]	13.046	2.250
57	uinst[13]	10.193	2.087
54	alu_op[3]	15.365	2.518

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C4	100.00%
R2C8	100.00%
R2C16	100.00%
R2C32	100.00%
R3C10	100.00%
R4C20	100.00%
R6C40	100.00%
R12C15	100.00%
R22C20	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name i_clk -period 37.04 -waveform {0 18.518} [get_ports {i_clk}] -add
TC_REPORT_TIMING	Actived	report_timing -hold -from_clock [get_clocks {i_clk}] -to_clock [get_clocks {i_clk}] -max_paths 25 -max_common_paths 1
TC_REPORT_TIMING	Actived	report_timing -setup -from_clock [get_clocks {i_clk}] -to_clock [get_clocks {i_clk}] -max_paths 25 -max_common_paths 1