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Optimized from Version1.03

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phdlee
2018-03-05 12:51:14 +09:00
parent bf68dd6c26
commit fb2c9d2cc3
5 changed files with 79 additions and 153 deletions
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11
ubitx_20/ubitx_si5351.ino
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@@ -60,6 +60,7 @@ void i2cWriten(uint8_t reg, uint8_t *vals, uint8_t vcnt) { // write array
Wire.endTransmission();
}
uint8_t si5351Val[8] = {0, 1, 0, 0, 0, 0, 0, 0}; //for reduce program memory size
void si5351bx_init() { // Call once at power-up, start PLLA
uint32_t msxp1;
@@ -68,11 +69,13 @@ void si5351bx_init() { // Call once at power-up, start PLLA
i2cWrite(3, si5351bx_clken); // Disable all CLK output drivers
i2cWrite(183, SI5351BX_XTALPF << 6); // Set 25mhz crystal load capacitance
msxp1 = 128 * SI5351BX_MSA - 512; // and msxp2=0, msxp3=1, not fractional
uint8_t vals[8] = {0, 1, BB2(msxp1), BB1(msxp1), BB0(msxp1), 0, 0, 0};
i2cWriten(26, vals, 8); // Write to 8 PLLA msynth regs
//uint8_t vals[8] = {0, 1, BB2(msxp1), BB1(msxp1), BB0(msxp1), 0, 0, 0};
si5351Val[2] = BB2(msxp1);
si5351Val[3] = BB1(msxp1);
si5351Val[4] = BB0(msxp1);
i2cWriten(26, si5351Val, 8); // Write to 8 PLLA msynth regs
i2cWrite(177, 0x20); // Reset PLLA (0x80 resets PLLB)
// for (reg=16; reg<=23; reg++) i2cWrite(reg, 0x80); // Powerdown CLK's
// i2cWrite(187, 0); // No fannout of clkin, xtal, ms0, ms4
}
void si5351bx_setfreq(uint8_t clknum, uint32_t fout) { // Set a CLK to fout Hz