mirror of
https://github.com/rfivet/stm32bringup.git
synced 2024-11-15 17:15:57 -05:00
224 lines
6.5 KiB
C
224 lines
6.5 KiB
C
/* clocks.c -- system layer
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** Copyright (c) 2020 Renaud Fivet
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**
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** clocks configuration: HSI, HSE, PLL HSI, PLL HSE
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** implements system.h interface
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** uptime = seconds elapsed since boot
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** SysClck 8MHz HSI based, baudrate 9600, Busy wait transmission
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** user LED toggled every second
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** SysTick interrupt every second
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*/
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#include "system.h" /* implements system.h */
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#define SYSTICK ((volatile long *) 0xE000E010)
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#define SYSTICK_CSR SYSTICK[ 0]
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#define SYSTICK_RVR SYSTICK[ 1]
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#define SYSTICK_CVR SYSTICK[ 2]
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#define CAT( a, b) a##b
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#define HEXA( a) CAT( 0x, a)
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#define RCC ((volatile long *) 0x40021000)
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#define RCC_CR RCC[ 0]
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#define RCC_CR_HSION 0x00000001 /* 1: Internal High Speed clock enable */
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#define RCC_CR_HSEON 0x00010000 /* 16: External High Speed clock enable */
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#define RCC_CR_HSERDY 0x00020000 /* 17: External High Speed clock ready flag */
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#define RCC_CR_PLLON 0x01000000 /* 24: PLL enable */
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#define RCC_CR_PLLRDY 0x02000000 /* 25: PLL clock ready flag */
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#define RCC_CFGR RCC[ 1]
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#define RCC_CFGR_SW_MSK 0x00000003 /* 1-0: System clock SWitch Mask */
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#define RCC_CFGR_SW_HSE 0x00000001 /* 1-0: Switch to HSE as system clock */
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#define RCC_CFGR_SW_PLL 0x00000002 /* 1-0: Switch to PLL as system clock */
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#define RCC_CFGR_SWS_MSK 0x0000000C /* 3-2: System clock SWitch Status Mask */
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#define RCC_CFGR_SWS_HSE 0x00000004 /* 3-2: HSE used as system clock */
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#define RCC_CFGR_SWS_PLL 0x00000008 /* 3-2: PLL used as system clock */
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#define RCC_CFGR_PLLSRC 0x00010000
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#define RCC_CFGR_PLLSRC_HSI 0x00000000 /* HSI / 2 */
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#define RCC_CFGR_PLLSRC_HSE 0x00010000 /* HSE */
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#define RCC_CFGR_PLLXTPRE 0x00020000
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#define RCC_CFGR_PLLXTPRE_DIV1 0x00000000 /* HSE */
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#define RCC_CFGR_PLLXTPRE_DIV2 0x00020000 /* HSE / 2 */
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#define RCC_CFGR_PLLMUL_MSK (0x00F << 18)
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#define RCC_CFGR_PLLMUL( v) ((v - 2) << 18)
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#define RCC_AHBENR RCC[ 5]
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#define RCC_AHBENR_IOP( h) (1 << (17 + HEXA( h) - 0xA))
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#define RCC_APB2ENR RCC[ 6]
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#define RCC_APB2ENR_USART1EN 0x00004000 /* 14: USART1 clock enable */
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#define GPIOA ((volatile long *) 0x48000000)
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#define GPIOB ((volatile long *) 0x48000400)
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#define GPIO( x) CAT( GPIO, x)
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#define MODER 0
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#define ODR 5
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#define AFRH 9
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#define USART1 ((volatile long *) 0x40013800)
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#define CR1 0 /* Config */
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#define BRR 3 /* Baudrate */
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#define ISR 7 /* Interrupt and Status */
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#define TDR 10 /* Transmit Data */
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#define USART_CR1_TE 8 /* 3: Transmit Enable */
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#define USART_CR1_RE 4 /* 2: Receive Enable */
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#define USART_CR1_UE 1 /* 0: USART Enable */
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#define USART_ISR_TXE (1 << 7) /* 7: Transmit Data Register Empty */
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/* user LED ON when PA4 is low */
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#define LED_IOP A
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#define LED_PIN 4
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#define LED_ON 0
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/* 8MHz quartz, configure PLL at 24MHz */
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#define HSE 8000000
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#define PLL 6
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#define BAUD 9600
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#ifdef PLL
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# ifdef HSE
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# define CLOCK HSE / 2 * PLL
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# else /* HSI */
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# define CLOCK 8000000 / 2 * PLL
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# endif
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# if CLOCK < 16000000
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# error PLL output below 16MHz
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# endif
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#else
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# ifdef HSE
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# define CLOCK HSE
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# else /* HSI */
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# define CLOCK 8000000
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# endif
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#endif
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#if CLOCK > 48000000
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# error clock frequency exceeds 48MHz
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#endif
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#if CLOCK % BAUD
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# warning baud rate not accurate at that clock frequency
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#endif
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void kputc( unsigned char c) { /* character output */
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static unsigned char lastc ;
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if( c == '\n' && lastc != '\r')
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kputc( '\r') ;
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/* Active wait while transmit register is full */
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while( (USART1[ ISR] & USART_ISR_TXE) == 0) ;
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USART1[ TDR] = c ;
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lastc = c ;
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}
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int kputs( const char s[]) { /* string output */
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int cnt = 0 ;
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int c ;
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while( (c = *s++) != 0) {
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kputc( c) ;
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cnt += 1 ;
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}
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return cnt ;
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}
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void yield( void) { /* give way */
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__asm( "WFI") ; /* Wait for System Tick Interrupt */
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}
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volatile unsigned uptime ; /* seconds elapsed since boot */
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#ifdef LED_ON
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static void userLEDtoggle( void) {
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GPIO( LED_IOP)[ ODR] ^= 1 << LED_PIN ; /* Toggle User LED */
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}
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#endif
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void SysTick_Handler( void) {
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uptime += 1 ;
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#ifdef LED_ON
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userLEDtoggle() ;
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#endif
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}
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int init( void) {
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/* By default SYSCLK == HSI [8MHZ] */
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#ifdef HSE
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/* Start HSE clock (8 MHz external oscillator) */
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RCC_CR |= RCC_CR_HSEON ;
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/* Wait for oscillator to stabilize */
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do {} while( (RCC_CR & RCC_CR_HSERDY) == 0) ;
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#endif
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#ifdef PLL
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/* Setup PLL HSx/2 * 6 [24MHz] */
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/* Default 0: PLL HSI/2 src, PLL MULL * 2 */
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# ifdef HSE
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RCC_CFGR = RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_DIV2 ;
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# endif
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RCC_CFGR |= RCC_CFGR_PLLMUL( PLL) ;
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RCC_CR |= RCC_CR_PLLON ;
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do {} while( (RCC_CR & RCC_CR_PLLRDY) == 0) ; /* Wait for PLL */
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/* Switch to PLL as system clock SYSCLK == PLL [24MHz] */
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MSK) | RCC_CFGR_SW_PLL ;
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do {} while( (RCC_CFGR & RCC_CFGR_SWS_MSK) != RCC_CFGR_SWS_PLL) ;
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#else
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# ifdef HSE
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/* Switch to HSE as system clock SYSCLK == HSE [8MHz] */
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MSK) | RCC_CFGR_SW_HSE ;
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do {} while( (RCC_CFGR & RCC_CFGR_SWS_MSK) != RCC_CFGR_SWS_HSE) ;
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# endif
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#endif
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#ifdef HSE
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/* Switch off HSI */
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RCC_CR &= ~RCC_CR_HSION ;
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#endif
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/* SYSTICK */
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SYSTICK_RVR = CLOCK / 8 - 1 ; /* HBA / 8 */
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SYSTICK_CVR = 0 ;
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SYSTICK_CSR = 3 ; /* HBA / 8, Interrupt ON, Enable */
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/* SysTick_Handler will execute every 1s from now on */
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#ifdef LED_ON
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/* User LED ON */
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RCC_AHBENR |= RCC_AHBENR_IOP( LED_IOP) ; /* Enable IOPx periph */
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GPIO( LED_IOP)[ MODER] |= 1 << (LED_PIN * 2) ; /* LED_IO Output [01],
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** over default 00 */
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/* OTYPER Push-Pull by default */
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/* Pxn output default LOW at reset */
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# if LED_ON
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userLEDtoggle() ;
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# endif
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#endif
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/* USART1 9600 8N1 */
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RCC_AHBENR |= RCC_AHBENR_IOP( A) ; /* Enable GPIOA periph */
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GPIOA[ MODER] |= 0x0A << (9 * 2) ; /* PA9-10 ALT 10, over default 00 */
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GPIOA[ AFRH] |= 0x110 ; /* PA9-10 AF1 0001, over default 0000 */
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RCC_APB2ENR |= RCC_APB2ENR_USART1EN ;
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USART1[ BRR] = CLOCK / BAUD ; /* PCLK is default source */
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USART1[ CR1] |= USART_CR1_UE | USART_CR1_TE ; /* Enable USART & Tx */
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kputs(
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#ifdef PLL
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"PLL"
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#endif
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#ifdef HSE
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"HSE"
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#else
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"HSI"
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#endif
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"\n") ;
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return 0 ;
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}
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/* end of clocks.c */
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