H. Peter Anvin 7f688841ce insns.dat: accept explicit ax/eax/rax operand to CLZERO ...

AMD documents this instruction with an rax operand. The error behavior
implies this is an address-size-sensitive instruction. Add support for
specifying the explicit operand, but consistent with normal ndisasm
behavior, don't disassemble the implicit operand.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>

2018-12-22 17:52:27 -08:00

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