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a3191aee77
Add documentation on how the new syntax elements related to APX work. Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
80 lines
3.1 KiB
Plaintext
80 lines
3.1 KiB
Plaintext
\C{APX} APX syntax
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Intel APX (Advanced Performance Extensions) introduces multiple new ways to
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invoke already available instructions but also implements a few new ones. The
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main additions are more GPRs (General Purpose Registers) - R16-R31, new modes
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that disable modyfing flags by instructions or disable zeroing out the upper
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parts of registers. Another big addition is giving many instructions a
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non-destructive destination operand - allowing saving the operation result to a
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separately specified register without modyfing the source registers. From newly
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added instructions there is a new double-conditional type that allows updating
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the CPU flags to any values if the first condition turns out to be false. Other
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important new instructions are push and pop variants that move two elements at a
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time to or from the stack, and an absolute jump that takes a full 64-bit
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immediate address.
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\H{egprs} Extended General Purpose Registers
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When it comes to register size, the new extended number of registers work the
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same way as registers R8-R15 (see \k{reg64}). So for example \c{r25d} would mean
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the 25th register, with 32 bit size. Using the extended register number
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automatically uses the APX encoding of an instruction. An EVEX prefix is used,
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unless an instruction can utilize the REX2 prefix, which is then preferable due
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to taking up less memory than EVEX. One can find instructions that can use the
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REX2 prefix by looking at the APX documentation, chapter 3.1.5, and finding
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instructions with Legacy-map 0 or 1.
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\H{ndd} New Data Destination
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Using the New Data Destination register is specified by adding an additional
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register in place of the first operand - for instructions that support it of
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course. So for example an add instruction could look like
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\c add rax, rbx, rcx
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which would add numbers stored in the B and C registers and store the result in
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A.
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\H{nfzu} Non-Modyfing and Zero-Upper flags
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The non-modyfing flags mode can be used with supported instructions by adding a
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{nf} suffix to the instruction mnemonic, for example
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\c add {nf} rax, rbx.
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In the same way the {zu} can be used meaning - "zero-upper", which disables
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zeroing out upper parts of GPRs when the operand size is 8 or 16 bits. For
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example
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\c setb {zu} ax
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will not zero out bits 63:16 in the A register.
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\H{dfv} Default Flags Value
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New SCC (Source Condition Code) instructions: CCMPSCC and CTESTSCC allow using
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the {dfv=} mnemonic suffix which can contain a list of comma separated CPU
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flags, specifically OF, SF, ZF, CF. Any given SCC instruction has a flag
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condition encoded in the mnemonic (for example CCMPB - compare if below). If the
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condition is true, the instruction does what it's supposed to (compare or test
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operands). If the condition is false the flags are modified to the values
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specified in the {dfv} list.
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\H{push2pop2} Push2 and Pop2
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The new push and pop instructions allow pushing or popping two values from the
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stack at once. The operands can only be registers, and the order of operation
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for an instruction:
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\c push2 rax, rbx
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translates into:
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\c push rax
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\c push rbx
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\H{jmpabs} JMPABS
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A new near jump instruction takes the absolute address that's subjected to
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canonicality checks.
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