H. Peter Anvin a0396faf3b Fix control/debug register patterns ...

The control and debug registers are always using the default operand
size. It is probably easiest to just encode it explicitly for now.

Control registers are particularly weird because of the AMD "lock as
REX.R" hack...

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>

2025-09-19 16:26:35 -07:00

..

bytecode.txt

Allow synthesis of ROLX

2025-09-13 21:25:02 -07:00

iflags.ph

assemble: apx: Add NF forbidden flag and fix SBB and ADC

2025-09-19 14:53:04 +02:00

insns-iflags.ph

insns: add PROT flag if either EVEX or LONG is set

2024-08-23 13:15:46 -07:00

insns.dat

Fix control/debug register patterns

2025-09-19 16:26:35 -07:00

insns.pl

BR 3392957: 64-bit K registers allowed in non-64-bit mode

2025-09-19 13:39:26 -07:00

preinsns.pl

Fix control/debug register patterns

2025-09-19 16:26:35 -07:00

regs.dat

ndisasm: make the assembler (hopefully) work again

2025-08-30 16:16:43 -07:00

regs.pl

ndisasm: make the assembler (hopefully) work again

2025-08-30 16:16:43 -07:00

rex2.pl

x86: add Perl script for rex2 compatibility testing (not yet used)

2025-03-04 08:43:09 -08:00

x86const.h

apx: modify the tokenizer to be able to handle {dfv=...}

2024-07-27 17:57:08 -07:00