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94923e1382
Split the RET instruction test by mode for ease of disassembly, and test more subcases. Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
79 lines
662 B
NASM
79 lines
662 B
NASM
;; All the flavors of RET
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bits 16
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ret
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retn
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retf
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retw
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retnw
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retfw
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retd
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retnd
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retfd
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o16 ret
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o16 retn
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o16 retf
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o32 ret
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o32 retn
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o32 retf
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%ifdef ERROR
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retq
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retnq
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retfq
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o64 ret
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o64 retn
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o64 retf
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%endif
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bits 32
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ret
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retn
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retf
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retw
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retnw
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retfw
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retd
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retnd
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retfd
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o16 ret
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o16 retn
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o16 retf
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o32 ret
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o32 retn
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o32 retf
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%ifdef ERROR
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retq
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retnq
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retfq
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o64 ret
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o64 retn
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o64 retf
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%endif
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bits 64
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ret
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retn
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retf ; Probably should have been RETFQ, but: legacy...
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retw
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retnw
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retfw
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o16 ret
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o16 retn
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o16 retf
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%ifdef ERROR
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retd
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retnd
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o32 ret
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o32 retn
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%endif
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retfd
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o32 retf
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retq
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retnq
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retfq
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o64 ret
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o64 retn
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o64 retf
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