mirror of
https://github.com/netwide-assembler/nasm.git
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172c4b2342
-- AVX-VNNI_INT{,8,16} instructions: VPDP{B,W}{SS,SU,US,UU}{D,DS}
- AVX-VNNI_INT{,8,16} test files
Checked with XED version: [v2025.06.08]
237 lines
10 KiB
Perl
237 lines
10 KiB
Perl
# -*- perl -*-
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#
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# Flags consumed by preinsns.pl/insns.pl and not actually present in
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# the generated C code:
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#
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# ND - not for disassembler
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# DISASM - disassembler only
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# KILL - ignore this instruction pattern entirely
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# !ZU - no zero-upper version of this instruction
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# !FL - instruction never modifies the flags
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# NF! - alias for NF_R: {nf} syntactic prefix required
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# SMx-y - alias for SMx,SMx+1,SMx+2,...,SMy
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#
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#
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# dword bound, index 0 - specific flags
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#
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if_align('IGEN', $NOBREAK);
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# The following MUST be in word 0
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if_("SM0", "Size match operand 0");
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if_("SM1", "Size match operand 1");
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if_("SM2", "Size match operand 2");
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if_("SM3", "Size match operand 3");
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if_("SM4", "Size match operand 4");
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if_("AR0", "SB, SW, SD applies to operand 0");
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if_("AR1", "SB, SW, SD applies to operand 1");
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if_("AR2", "SB, SW, SD applies to operand 2");
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if_("AR3", "SB, SW, SD applies to operand 3");
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if_("AR4", "SB, SW, SD applies to operand 4");
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# These must match the order of the BITSx flags in opflags.h
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# Are these obsolete?
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if_("SB", "Unsized operands can't be non-byte");
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if_("SW", "Unsized operands can't be non-word");
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if_("SD", "Unsized operands can't be non-dword");
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if_("SQ", "Unsized operands can't be non-qword");
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if_("ST", "Unsized operands can't be non-tword");
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if_("SO", "Unsized operands can't be non-oword");
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if_("SY", "Unsized operands can't be non-yword");
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if_("SZ", "Unsized operands can't be non-zword");
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# End BITSx order match requirement
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if_("NWSIZE", "Operand size defaults to 64 in 64-bit mode");
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if_("OSIZE", "Unsized operands must match the default operand size");
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if_("ASIZE", "Unsized operands must match the address size");
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if_("ANYSIZE", "Ignore operand size even if explicit");
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if_("SX", "Unsized operands not allowed");
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if_("SDWORD", "Strict sdword64 matching");
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if_break_ok();
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if_("PSEUDO", "Pseudo-instruction (directive)");
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if_("JMP_RELAX", "Relaxable jump instruction");
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if_("JCC_HINT", "Hintable jump instruction");
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if_("OPT", "Optimizing assembly only");
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if_("LATEVEX", "Only if EVEX instructions are disabled");
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if_("NOREX", "Instruction does not support REX encoding");
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if_("NOAPX", "Instruction does not support APX registers or REX2");
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if_("NF", "Instruction supports the {nf} prefix");
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if_("NF_R", "Instruction requires the {nf} prefix");
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if_("NF_N", "Instruction doesn't allow the {nf} prefix");
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if_("NF_E", "EVEX.NF set with {nf} prefix");
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if_("ZU", "Instruction supports the {zu} prefix");
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if_("ZU_R", "Instruction requires the {zu} prefix");
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if_("ZU_E", "EVEX.ND set with {zu} prefix");
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if_("LIG", "Ignore VEX/EVEX L field");
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if_("WIG", "Ignore VEX/EVEX W field");
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if_("WW", "VEX/EVEX W is REX.W");
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if_("SIB", "SIB encoding required");
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if_("LOCK", "Lockable if operand 0 is memory");
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if_("LOCK1", "Lockable if operand 1 is memory");
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if_("NOLONG", "Not available in long mode");
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if_("LONG", "Long mode");
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if_("NOHLE", "HLE prefixes forbidden");
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if_("MIB", "split base/index EA");
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if_("BND", "BND (0xF2) prefix available");
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if_("REX2", "REX2 encoding required");
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if_("HLE", "HLE prefixed");
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if_("FL", "Instruction modifies the flags");
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if_("MOPVEC", "M operand is a vector"); # Autodetected
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if_("SCC", "EVEX[27:24] is special condition code");
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if_("BESTDIS", "Preferred disassembly pattern");
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#
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# Special immediates types like {dfv=}
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# Used to detect incorrect usage and for the disassembler.
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#
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if_("DFV", "Destination flag values");
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#
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# dword bound - instruction feature filtering flags
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#
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if_align('FEATURE');
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#
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# Encoding formats that can be set with the CPU directive
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#
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if_("VEX", "VEX or XOP encoded instruction");
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if_("EVEX", "EVEX encoded instruction");
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#
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# Feature filtering flags
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#
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if_("PRIV", "Privileged instruction");
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if_("SMM", "Only valid in SMM");
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if_("PROT", "Protected mode only");
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if_("UNDOC", "Undocumented");
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if_("FPU", "FPU");
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if_("MMX", "MMX");
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if_("3DNOW", "3DNow!");
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if_("SSE", "SSE (KNI, MMX2)");
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if_("SSE2", "SSE2");
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if_("SSE3", "SSE3 (PNI)");
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if_("VMX", "VMX");
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if_("SSSE3", "SSSE3");
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if_("SSE4A", "AMD SSE4a");
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if_("SSE41", "SSE4.1");
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if_("SSE42", "SSE4.2");
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if_("SSE5", "SSE5");
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if_("AVX", "AVX (256-bit floating point)");
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if_("AVX2", "AVX2 (256-bit integer)");
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if_("FMA", "Fused multiply-add");
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if_("BMI1", "Bit manipulation instructions 1");
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if_("BMI2", "Bit manipulation instructions 2");
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if_("TBM", "");
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if_("RTM", "");
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if_("AVX512", "AVX-512");
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if_("AVX512F", "AVX-512F (base architecture)");
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if_("AVX512CD", "AVX-512 Conflict Detection");
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if_("AVX512ER", "AVX-512 Exponential and Reciprocal");
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if_("AVX512PF", "AVX-512 Prefetch");
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if_("MPX", "MPX");
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if_("SHA", "SHA");
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if_("AVX512VL", "AVX-512 Vector Length Orthogonality");
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if_("AVX512DQ", "AVX-512 Dword and Qword");
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if_("AVX512BW", "AVX-512 Byte and Word");
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if_("AVX512IFMA", "AVX-512 IFMA instructions");
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if_("AVX512VBMI", "AVX-512 VBMI instructions");
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if_("AES", "AES instructions");
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if_("VAES", "AES AVX instructions");
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if_("VPCLMULQDQ", "AVX Carryless Multiplication");
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if_("GFNI", "Galois Field instructions");
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if_("AVX512VBMI2", "AVX-512 VBMI2 instructions");
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if_("AVX512VNNI", "AVX-512 VNNI instructions");
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if_("AVX512BITALG", "AVX-512 Bit Algorithm instructions");
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if_("AVX512VPOPCNTDQ", "AVX-512 VPOPCNTD/VPOPCNTQ");
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if_("AVX5124FMAPS", "AVX-512 4-iteration multiply-add");
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if_("AVX5124VNNIW", "AVX-512 4-iteration dot product");
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if_("AVX512FP16", "AVX-512 FP16 instructions");
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if_("AVX512FC16", "AVX-512 FC16 instructions");
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if_("SGX", "Intel Software Guard Extensions (SGX)");
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if_("CET", "Intel Control-Flow Enforcement Technology (CET)");
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if_("ENQCMD", "Enqueue command instructions");
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if_("TSXLDTRK", "TSX suspend load address tracking");
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if_("AVX512BF16", "AVX-512 bfloat16");
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if_("AVX512VP2INTERSECT", "AVX-512 VP2INTERSECT instructions");
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if_("AMXTILE", "AMX tile configuration instructions");
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if_("AMXBF16", "AMX bfloat16 multiplication");
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if_("AMXFP16", "AMX FP16 multiplication");
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if_("AMXINT8", "AMX 8-bit integer multiplication");
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if_("AMXCOMPLEX", "AMX float16 complex multiplication");
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if_("FRED", "Flexible Return and Exception Delivery (FRED)");
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if_("RAOINT", "Remote atomic operations (RAO-INT)");
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if_("UINTR", "User interrupts");
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if_("CMPCCXADD", "CMPccXADD instructions");
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if_("PREFETCHI", "PREFETCHI0 and PREFETCHI1");
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if_("MSRLIST", "RDMSRLIST and WRMSRLIST");
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if_("AVXNECONVERT", "AVX exceptionless floating-point conversions");
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if_("AVXVNNI", "AVX Vector Neural Network instructions");
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if_("AVXVNNIINT8", "AVX Vector Neural Network 8-bit integer instructions");
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if_("AVXVNNIINT16", "AVX Vector Neural Network 16-bit integer instructions");
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if_("AVXIFMA", "AVX integer multiply and add");
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if_("HRESET", "History reset");
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if_("SMAP", "Supervisor Mode Access Prevention (SMAP)");
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if_("SHA512", "SHA512 instructions");
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if_("HSM3", "SM3 hash instructions");
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if_("HSM4", "SM4 hash instructions");
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if_("APX", "Advanced Performance Extensions (APX)");
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if_("AVX10_1", "AVX 10.1 instructions");
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if_("AVX10_2", "AVX 10.2 instructions");
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if_("AVX10_VNNIINT", "AVX Vector Neural Network integer instructions");
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if_("ADX", "ADCX and ADOX instructions");
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if_("PKU", "Protection key for user mode");
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if_("MONITOR", "MONITOR and MWAIT");
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if_("MONITORX", "MONITORX and MWAITX");
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if_("WAITPKG", "User wait instruction package");
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if_("MSR_IMM", "Immediate RDMSR/WRMSRNS instructions");
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if_("AESKLE", "AES key locker");
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if_("AESKLEWIDE_KL", "AES wide key locker");
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# Single-instruction CPUID bits without additional help text
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my @oneins = qw(invpcid prefetchwt1 pbndkb pconfig wbnoinvd serialize
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lkgs wrmsrns clflushopt clwb rdrand rdseed rdpid lzcnt
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ptwrite cldemote movdiri movdir64b clzero movbe movrs);
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foreach my $ins (@oneins) {
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if_($ins, "\U$ins\E instruction");
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}
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# Put these last to minimize their relevance
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if_("OBSOLETE", "Instruction removed from architecture");
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if_("NEVER", "Instruction never implemented");
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if_("NOP", "Instruction is always a (nonintentional) NOP");
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#
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# dword bound - cpu type flags
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#
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# The CYRIX and AMD flags should have the highest bit values; the
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# disassembler selection algorithm depends on it.
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#
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if_align('CPU');
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if_("8086", "8086");
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if_("186", "186+");
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if_("286", "286+");
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if_("386", "386+");
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if_("486", "486+");
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if_("PENT", "Pentium");
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if_("P6", "P6");
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if_("KATMAI", "Katmai");
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if_("WILLAMETTE", "Willamette");
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if_("PRESCOTT", "Prescott");
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if_("IA64", "IA64 (in x86 mode)");
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if_("X86_64", "x86-64 (long or legacy mode)");
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if_("NEHALEM", "Nehalem");
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if_("WESTMERE", "Westmere");
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if_("SANDYBRIDGE", "Sandy Bridge");
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if_("FUTURE", "Ivy Bridge or newer");
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# Default CPU level
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if_("DEFAULT", "Default CPU level");
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# Must be the last CPU definition
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if_("ANY", "Allow any known instruction");
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# These must come after the CPU definitions proper
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if_("CYRIX", "Cyrix-specific");
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if_("AMD", "AMD-specific");
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